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TMS320F28375DPZP Datasheet(PDF) 106 Page - Texas Instruments |
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TMS320F28375DPZP Datasheet(HTML) 106 Page - Texas Instruments |
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106 / 226 page  8.10.1.2.4 ADC Characteristics (12-Bit Single-Ended Mode) over recommended operating conditions (unless otherwise noted)(5) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC conversion cycles(1) 10.1 11 ADCCLKs Power-up time 500 µs Gain error –5 ±3 5 LSBs Offset error –4 ±2 4 LSBs Channel-to-channel gain error ±4 LSBs Channel-to-channel offset error ±2 LSBs ADC-to-ADC gain error Identical VREFHI and VREFLO for all ADCs ±4 LSBs ADC-to-ADC offset error Identical VREFHI and VREFLO for all ADCs ±2 LSBs DNL(2) > –1 ±0.5 1 LSBs INL –2 ±1.0 2 LSBs SNR(3) (10) VREFHI = 2.5 V, fin = 100 kHz 68.8 dB THD(3) (10) VREFHI = 2.5 V, fin = 100 kHz –78.4 dB SFDR(3) (10) VREFHI = 2.5 V, fin = 100 kHz 79.2 dB SINAD(3) (10) VREFHI = 2.5 V, fin = 100 kHz 68.4 dB ENOB(3) (10) VREFHI = 2.5 V, fin = 100 kHz, single ADC(6), all packages 11.1 bits VREFHI = 2.5 V, fin = 100 kHz, synchronous ADCs(7), all packages 11.1 VREFHI = 2.5 V, fin = 100 kHz, asynchronous ADCs(8), 100-pin PZP package Not supported VREFHI = 2.5 V, fin = 100 kHz, asynchronous ADCs(8), 176-pin PTP package 9.7 VREFHI = 2.5 V, fin = 100 kHz, asynchronous ADCs(8), 337-ball ZWT package 10.9 PSRR VDDA = 3.3-V DC + 200 mV DC up to Sine at 1 kHz 60 dB PSRR VDDA = 3.3-V DC + 200 mV Sine at 800 kHz 57 dB ADC-to-ADC isolation(10) (4) (9) VREFHI = 2.5 V, synchronous ADCs(7), all packages –1 1 LSBs VREFHI = 2.5 V, asynchronous ADCs(8), 100-pin PZP package Not supported VREFHI = 2.5 V, asynchronous ADCs(8), 176-pin PTP package –9 9 VREFHI = 2.5 V, asynchronous ADCs(8), 337-ball ZWT package –2 2 VREFHI input current 130 µA (1) See Section 8.10.1.2.7. (2) No missing codes. (3) AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source. (4) Maximum DC code deviation due to operation of multiple ADCs simultaneously. (5) Typical values are measured with VREFHI = 2.5 V and VREFLO = 0 V. Minimum and Maximum values are tested or characterized with VREFHI = 2.5 V and VREFLO = 0 V. (6) One ADC operating while all other ADCs are idle. (7) All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution. TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021 www.ti.com 106 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMS320F28379D TMS320F28379D-Q1 TMS320F28378D TMS320F28377D TMS320F28377D-Q1 TMS320F28376D TMS320F28375D TMS320F28374D |
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