TMS320F28375DPZP datasheet(109/226 Pages) TI

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8.10.1.2.7 ADC Timing Diagrams

Section 8.10.1.2.7.1 lists the ADC timings in 12-bit mode (SYSCLK cycles). Section 8.10.1.2.7.2 lists the ADC

timings in 16-bit mode. Figure 8-35 and Figure 8-36 show the ADC conversion timings for two SOCs given the

following assumptions:

• SOC0 and SOC1 are configured to use the same trigger.

• No other SOCs are converting or pending when the trigger occurs.

• The round robin pointer is in a state that causes SOC0 to convert first.

• ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag

propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE module).

Table 8-9 lists the descriptions of the ADC timing parameters that are in Figure 8-35 and Figure 8-36 .

Table 8-9. ADC Timing Parameters

PARAMETER

DESCRIPTION

tSH

The duration of the S+H window.

At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital

value. The duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each

SOC, so tSH will not necessarily be the same for different SOCs.

Note: The value on the S+H capacitor will be captured approximately 5 ns before the end of the S+H window

regardless of device clock settings.

tLAT

The time from the end of the S+H window until the ADC conversion results latch in the ADCRESULTx register.

If the ADCRESULTx register is read before this time, the previous conversion results will be returned.

tEOC

The time from the end of the S+H window until the next ADC conversion S+H window can begin. The

subsequent sample can start before the conversion results are latched.

tINT

The time from the end of the S+H window until an ADCINT flag is set (if configured).

If the INTPULSEPOS bit in the ADCCTL1 register is set, tINT will coincide with the conversion results being

latched into the result register.

If the INTPULSEPOS bit is 0, tINT will coincide with the end of the S+H window. If tINT triggers a read of the

ADC result register (directly through DMA or indirectly by triggering an ISR that reads the result), care must be

taken to ensure the read occurs after the results latch (otherwise, the previous results will be read).

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TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D

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SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021

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TMS320F28375DPZP Datasheet(PDF) 109 Page - Texas Instruments