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TMS320F28375DPZP Datasheet(PDF) 168 Page - Texas Instruments |
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TMS320F28375DPZP Datasheet(HTML) 168 Page - Texas Instruments |
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168 / 226 page  8.12.5.1.2 SPI Slave Mode Timings Section 8.12.5.1.2.1 lists the SPI slave mode timing requirements. Section 8.12.5.1.2.2 lists the SPI slave mode switching characteristics. Figure 8-74 shows the SPI slave mode external timing where the clock phase = 0. Figure 8-75 shows the SPI slave mode external timing where the clock phase = 1. 8.12.5.1.2.1 SPI Slave Mode Timing Requirements NO. MIN MAX UNIT 12 tc(SPC)S Cycle time, SPICLK 4tc(SYSCLK) ns 13 tw(SPC1)S Pulse duration, SPICLK, first pulse 2tc(SYSCLK) – 1 ns 14 tw(SPC2)S Pulse duration, SPICLK, second pulse 2tc(SYSCLK) – 1 ns 19 tsu(SIMO)S Setup time, SPISIMO valid before SPICLK 1.5tc(SYSCLK) ns 20 th(SIMO)S Hold time, SPISIMO valid after SPICLK 1.5tc(SYSCLK) ns 25 tsu(STE)S Setup time, SPISTE valid before SPICLK (Clock Phase = 0) 2tc(SYSCLK) + 4 ns Setup time, SPISTE valid before SPICLK (Clock Phase = 1) 2tc(SYSCLK) + 14 ns 26 th(STE)S Hold time, SPISTE invalid after SPICLK 1.5tc(SYSCLK) ns 8.12.5.1.2.2 SPI Slave Mode Switching Characteristics over recommended operating conditions (unless otherwise noted) NO. PARAMETER MIN MAX UNIT High Speed Mode 15 td(SOMI)S Delay time, SPICLK to SPISOMI valid 9 ns 16 tv(SOMI)S Valid time, SPISOMI valid after SPICLK 0 ns Normal Mode 15 td(SOMI)S Delay time, SPICLK to SPISOMI valid 20 ns 16 tv(SOMI)S Valid time, SPISOMI valid after SPICLK 0 ns TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021 www.ti.com 168 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMS320F28379D TMS320F28379D-Q1 TMS320F28378D TMS320F28377D TMS320F28377D-Q1 TMS320F28376D TMS320F28375D TMS320F28374D |
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