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TMS320F28375DPZP Datasheet(PDF) 166 Page - Texas Instruments |
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TMS320F28375DPZP Datasheet(HTML) 166 Page - Texas Instruments |
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166 / 226 page  over recommended operating conditions (unless otherwise noted) NO. PARAMETER (BRR + 1) CONDITION(1) MIN MAX UNIT High Speed Mode 4 td(SIMO)M Delay time, SPICLK to SPISIMO valid Even, Odd 1 ns 5 tv(SIMO)M Valid time, SPISIMO valid after SPICLK Even 0.5tc(SPC)M – 2 ns Odd 0.5tc(SPC)M –0.5tc(LSPCLK) – 2 Normal Mode 4 td(SIMO)M Delay time, SPICLK to SPISIMO valid Even, Odd 6 ns 5 tv(SIMO)M Valid time, SPISIMO valid after SPICLK Even 0.5tc(SPC)M – 5 ns Odd 0.5tc(SPC)M –0.5tc(LSPCLK) – 5 (1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is greater than 3. 8.12.5.1.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1) over recommended operating conditions (unless otherwise noted) NO. PARAMETER (BRR + 1) CONDITION(1) MIN MAX UNIT General 1 tc(SPC)M Cycle time, SPICLK Even 4tc(LSPCLK) 128tc(LSPCLK) ns Odd 5tc(LSPCLK) 127tc(LSPCLK) 2 tw(SPCH)M Pulse duration, SPICLK, first pulse Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1 ns Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1 0.5tc(SPC)M – 0.5tc(LSPCLK) + 1 3 tw(SPC2)M Pulse duration, SPICLK, second pulse Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1 ns Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1 0.5tc(SPC)M + 0.5tc(LSPCLK) + 1 23 td(SPC)M Delay time, SPISTE valid to SPICLK Even, Odd 2tc(SPC)M – 3tc(SYSCLK) – 7 2tc(SPC)M – 3tc(SYSCLK) + 5 ns 24 tv(STE)M Valid time, SPICLK to SPISTE invalid Even – 7 +5 ns Odd – 7 +5 High Speed Mode 4 td(SIMO)M Delay time, SPISIMO valid to SPICLK Even 0.5tc(SPC)M – 1 ns Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1 5 tv(SIMO)M Valid time, SPISIMO valid after SPICLK Even 0.5tc(SPC)M – 2 ns Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 2 Normal Mode 4 td(SIMO)M Delay time, SPISIMO valid to SPICLK Even 0.5tc(SPC)M – 5 ns Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 5 5 tv(SIMO)M Valid time, SPISIMO valid after SPICLK Even 0.5tc(SPC)M – 5 ns Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 5 (1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is greater than 3. TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021 www.ti.com 166 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMS320F28379D TMS320F28379D-Q1 TMS320F28378D TMS320F28377D TMS320F28377D-Q1 TMS320F28376D TMS320F28375D TMS320F28374D |
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