TMS320F28375DPZP datasheet(163/226 Pages) TI

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8.12.5 Serial Peripheral Interface (SPI)

The SPI is a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed

length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is

normally used for communications between the microcontroller and external peripherals or another controller.

Typical applications include external I/O or peripheral expansion through devices such as shift registers, display

drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI. The

port supports 16-level receive and transmit FIFOs for reducing CPU servicing overhead.

The SPI module features include:

• SPISOMI: SPI slave-output/master-input pin

• SPISIMO: SPI slave-input/master-output pin

• SPISTE: SPI slave transmit-enable pin

• SPICLK: SPI serial-clock pin

• Two operational modes: master and slave

• Baud rate: 125 different programmable rates

• Data word length: 1 to 16 data bits

• Four clocking schemes (controlled by clock polarity and clock phase bits) include:

– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the

SPICLK signal and receives data on the rising edge of the SPICLK signal.

– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling

edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the

SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising

edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.

• Simultaneous receive-and-transmit operation (transmit function can be disabled in software)

• Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.

• 16-level transmit and receive FIFO

• Delayed transmit control

• 3-wire SPI mode

• SPISTE inversion for digital audio interface receive mode on devices with two SPI modules

• DMA support

• High-speed mode for up to 50-MHz full-duplex communication

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TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D

TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021

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TMS320F28375DPZP Datasheet(PDF) 163 Page - Texas Instruments