TMS320F28375DPZP datasheet(160/226 Pages) TI

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8.12.4 Serial Communications Interface (SCI)

The SCI is a 2-wire asynchronous serial port, commonly known as a UART. The SCI module supports digital

communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero

(NRZ) format

The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and each has

its own separate enable and interrupt bits. Both can be operated independently for half-duplex communication,

or simultaneously for full-duplex communication. To specify data integrity, the SCI checks received data for break

detection, parity, overrun, and framing errors. The bit rate is programmable to different speeds through a 16-bit

baud-select register. Figure 8-70 shows the SCI block diagram.

Features of the SCI module include:

• Two external pins:

– SCITXD: SCI transmit-output pin

– SCIRXD: SCI receive-input pin

Note

NOTE: Both pins can be used as GPIO if not used for SCI.

– Baud rate programmable to 64K different rates

• Data-word format

– One start bit

– Data-word length programmable from 1 to 8 bits

– Optional even/odd/no parity bit

– 1 or 2 stop bits

• Four error-detection flags: parity, overrun, framing, and break detection

• Two wakeup multiprocessor modes: idle-line and address bit

• Half- or full-duplex operation

• Double-buffered receive and transmit functions

• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with

status flags.

– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY

flag (transmitter-shift register is empty)

– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break

condition occurred), and RX ERROR flag (monitoring four interrupt conditions)

• Separate enable bits for transmitter and receiver interrupts (except BRKDT)

• NRZ format

• Auto baud-detect hardware logic

• 16-level transmit and receive FIFO

Note

All registers in this module are 8-bit registers. When a register is accessed, the register data is in the

lower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the upper byte has no

effect.

TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D

TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021

www.ti.com

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TMS320F28375DPZP Datasheet(PDF) 160 Page - Texas Instruments

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