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TMS320F28375DPZP Datasheet(PDF) 158 Page - Texas Instruments |
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TMS320F28375DPZP Datasheet(HTML) 158 Page - Texas Instruments |
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158 / 226 page  NO. MIN MAX UNIT na tskew(CKX-Data) Worst skew between Clock and Data to ensure GBD for sampled clock and datas ns CLKSTP = 10b, CLKXP = 0 M30 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 8P – 10 ns M31 th(CKXL-DRV) Hold time, DR valid after CLKX low 8P – 10 ns M32 tsu(BFXL-CKXH) Setup time, FSX low before CLKX high 8P+10 ns CLKSTP = 11b, CLKXP = 0 M39 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 8P – 10 ns M40 th(CKXH-DRV) Hold time, DR valid after CLKX high 8P – 10 ns M41 tsu(FXL-CKXH) Setup time, FSX low before CLKX high 16P+10 ns CLKSTP = 10b, CLKXP = 1 M49 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 8P – 10 ns M50 th(CKXH-DRV) Hold time, DR valid after CLKX high 8P – 10 ns M51 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 8P+10 ns CLKSTP = 11b, CLKXP = 1 M58 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 8P – 10 ns M59 th(CKXL-DRV) Hold time, DR valid after CLKX low 8P – 10 ns M60 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 16P+10 ns (1) CLKG should be configured to LSPCLK/2 by setting CLKSM = 1 and CLKGDV = 1 (2) For SPI slave modes CLKX must be a minimum of 8 CLKG cycles 8.12.3.1.2.4 McBSP as SPI Slave Switching Characteristics over operating free-air temperature range (unless otherwise noted) NO. PARAMETER MIN TYP MAX UNIT CLOCK 2P Cycle time, CLKG ns CLKSTP = 10b, CLKXP = 0 M26 td(CLKXH-DXV) Delay time, CLKX high to DX valid 3P + 6 5P + 20 ns M28 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 6P + 6 ns M29 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 6 ns CLKSTP = 11b, CLKXP = 0 M36 td(CLKXL-DXV) Delay time, CLKX low to DX valid 3P + 6 5P + 20 ns M37 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 7P + 6 ns M38 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 6 ns CLKSTP = 10b, CLKXP = 1 M45 td(CLKXL-DXV) Delay time, CLKX low to DX valid 3P + 6 5P + 20 ns M47 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 6P + 6 ns M48 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 6 ns CLKSTP = 11b, CLKXP = 1 M55 td(CLKXH-DXV) Delay time, CLKX high to DX valid 3P + 6 5P + 20 ns M56 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 7P + 6 ns M57 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 6 ns TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021 www.ti.com 158 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMS320F28379D TMS320F28379D-Q1 TMS320F28378D TMS320F28377D TMS320F28377D-Q1 TMS320F28376D TMS320F28375D TMS320F28374D |
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