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DP8496 Datasheet(PDF) 78 Page - National Semiconductor (TI) |
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DP8496 Datasheet(HTML) 78 Page - National Semiconductor (TI) |
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78 / 92 page ![]() 70 AC Specifications (Continued) 714 DISK WRITE DATA AND WRITE GATE TIMING TLF11212 – 48 ID Symbol Parameter Min Max Units 141 rcwch RCLK to WCLK High (Note 1) 15 ns 142 rcwcl RCLK to WCLK Low (Note 1) 15 ns 143 rcwga RCLK to Write Gate Asserted 15 ns 144 rcwgd RCLK to Write Gate Deasserted 18 ns 145 wds Write Data Setup to WCLK (Note 2) rcl b 5ns 146 wdh Write Data Hold from WCLK (Note 2) rch b 5ns Note 1 The absolute value of rcwch–rcwcl is 5 ns (max) Note 2 rcl refers to the RCLK low time in use rch refers to the RCLK high time in use This formula is tested ony at the frequencies listed in Table 81 Note 3 The WCLK transitions start before the WGATE is asserted and three cycles occur before WGATE assertion 715 DISK ADDRESS MARK (PSEUDO-HARD SECTORED FORMAT) TLF11212 – 49 ID Symbol Parameter Min Max Units 151 came RCLK to Address Mark Enable 15 ns 152 amfs Address Mark Found Setup to RCLK 10 ns 716 SCSI RESET TLF11212 – 50 ID Symbol Parameter Min Max Units 161 srst SCSI RST to All SCSI Lines Undriven 600 ns 162 rstw SCSI RST Width (Note 1) 2 bcp ns Note 1 bcp refers to the BCLK period in use This formula is tested only at the frequencies listed in Table 81 All SCSI signals are active-high on the DP8497 78 |
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