VSC8658 datasheet(45/95 Pages) MICROSEMI

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Configuration

VMDS-10242 VSC8658 Datasheet Revision 4.1

The following information applies to the extended control and status bits:

•

When bit 22.15 is set, the link integrity state machine is bypassed and the PHY is forced into a link

pass status.

•

When bits 22.11:0 are set to 00, the squelch threshold levels are based on the IEEE standard for

10BASE-T. When set to 01, the squelch level is decreased, which may improve the bit error rate

performance on long loops. When set to 10, the squelch level is increased and may improve the bit

error rate in high-noise environments.

•

When bit 22.9 is set, all sticky register bits retain their values during a software reset. Clearing this

bit causes all sticky register bits to change to their default values upon software reset. Super-sticky

bits retain their values upon software reset regardless of the setting of bit 22.9.

•

When bit 22.0 is set, if a write to any PHY register (registers 0 through 31, including extended

registers), the same write is broadcast to all PHYs. For example, if bit 22.0 is set to 1 and a write to

PHY_0 is executed (register 0 is set to 0x1040), all PHYs’ register 0s are set to 0x1040. Disabling

this bit restores normal PHY write operation. Reads are still possible when this bit is set, but the

value that is read corresponds only to the particular PHY being addressed.

5.2.18

Extended PHY Control Set 1

The bits in the extended control set control the MAC auto-negotiation function, the 100BASE-FX SerDes

function, and report SGMII alignment errors and EEPROM status. The following table shows the settings

available.

10BASE-T link

status

1 = 10BASE-T link active.

5:1

Reserved

SMI broadcast

write

R/W

This is a sticky bit.

1 = Enabled.

Table 27 •

Extended PHY Control 1, Address 23 (0x17)

Bit

Name

Access Description

Default

15:14

Reserved

MAC interface

auto-negotiation

R/W

This is a super-sticky bit.

1 = Enabled.

CMODE

MAC interface mode R/W

This is a super-sticky bit.

1 = 1000BASE-X.

0 = SGMII.

AMS preference

R/W

This is a super-sticky bit.

1 = Cat5 copper preferred.

0 = SerDes fiber/SFP preferred.

Table 26 •

Extended Control and Status, Address 22 (0x16) (continued)

Bit

Name

Access

Description

Default

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