VSC8658 datasheet(93/95 Pages) MICROSEMI

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Design Considerations

VMDS-10242 VSC8658 Datasheet Revision 4.1

Design Considerations

This section provides information about design issues for the VSC8658 device.

9.1

PHY Address ID (Register 23E, Bits 15 to 11)

Issue: The PHY Address ID in Register 23E does not function as intended. It can only indicate the

physical PHY port numbers 0 through 7 instead of those set through the CMODE pins.

Implications: A user needs to be aware that this address only represents the physical port number as

opposed to the actually PHY address on the MDC/MDIO bus.

Workaround: Software needing this feature must detect which specific device it is communicating to and

add a necessary offset to the address value to process the correct address.

9.2

JTAG Input High Voltage at 2.1 V

Issue: The JTAG pins do not meet the VIH(min) requirements of the CMOS and LVTTL standards. At

certain PVT corners, the minimum is 2.1 V.

Implications: None.

Workaround: None.

9.3

First SMI Write Fails After Software Reset

Issue: After applying software reset (using either register 0, bit 15 or the NSRESET pin), the first

subsequent SMI write operation into register 4 (auto-negotiation advertisement) or register 9

(1000BASE-T control) does not work. This issue only occurs if the first SMI write after software reset is

into register 4 or 9. This issue does not occur if any kind of SMI transaction (either read or write) is

applied to any register between the time of the software reset and the SMI write into register 4 or 9.

Implications: The PHY may operate unexpectedly, because settings for registers 4 and 9 remain at the

reset value. There are no such implications after either hardware reset or power-down events.

Workaround: Writing “0x0000” into register 31 after every software reset avoids this issue, and

subsequent SMI writes into register 4 or 9 succeed.

9.4

LED3 Port 7 Coupling Issue into XTAL Clock Pin

Issue: Whenever LED3 Port 7 blinks, the resulting noise couples into the XTAL clock input pin. This

causes additional noise on the transmit SerDes interface in the form of transmit jitter. In this case,

transmit jitter increases to a value in the range of 360 ps to 380 ps. This behavior is not seen with other

LED pins.

Implications: Using both the LED3 Port 7 and XTAL pins causes a higher level of transmit jitter on the

SerDes interface of the device.

Workaround: For better performance, avoid using the LED3 Port 7 pin as an LED indication.

9.5

100BASE-FX Clock Data Recovery Improvement

Issue: It is possible to improve the overall receive data performance in 100BASE-FX media by changing

the standard settings for the Clock Data Recovery (CDR) block.

Implications: While there is a low chance of seeing an issue in 100BASE-FX, it is recommended to

implement this script.

Workaround: There is a software workaround for this problem that can improve the 100BASE-FX CDR.

Change the CDR settings using the following script at PHY initialization time:

PhyWrite( PortNo, Register (dec), 16_bit_unsigned_data(hex) );

16_bit_unsigned_data = PhyRead( PortNo, Register (dec) );

VSC8658 Datasheet(PDF) 93 Page - Microsemi Corporation

VSC8658 Datasheet(HTML) 93 Page - Microsemi Corporation

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