L99LDLH32 datasheet(22/141 Pages) STMICROELECTRONICS

22 / 141 page

Functional description

L99LDLH32

22/141

DS12879 Rev 5

Figure 6. Device state diagram

Note:

Partial networking feature is not supported by the device. Mixed state on the bus has to be

avoided. In case devices are sent to initialization / stand by mode NOT through a broadcast

“send to sleep” command, the first UNICAST response frame of the device after wakeup

has to be ignored.

5.1.1

Stand-by mode

The pre-requisite for this mode is:



Device in initialization phase

The device enters Standby mode under the following condition:



By default, once the device is powered (VS present) and leaves initialization phase

(VS > VS_POR_H)

The Standby mode characteristics are:



Shadow register (a) preserved



RAM cleared



VS > VS_POR_H



V3V3 < V3V3_POR_L



VS low consumption



CAN FD Light compatible Interface inactive

Standby Mode

VS>VS_POR_H

V3V3<V3V3_POR_L

Shadow registers preserved

Low VS consumption

Serial Interface inactive

RAM cleared

Normal/Bus

Mode

Device operates according to

RAM ctrl register settings

Send

sleep

through

CAN

BUSMODE

= 0

and

GOSTBY

= 1

Dedicated Serial Interface commands:

WD_FAIL Read & Clear

BUSMODE = 1 and GOSTBY =0

Initialization

VS>VS_POR_H

V3V3>V3V3_POR_H

Shadow Registers loaded from

FTP

Serial Interface inactive

Outputs disabled

Startup Transition

VS > VS_POR_H

tSTARTUP

V3V3<V3V3_POR_L

** register 1Ah: Chain ID &

Position content preserved

All states

VS < VS_POR_L

OFF

All functions off. Reset of

Shadow Registers and

Fail Safe/

Stand Alone

Device operates according to FTP setting and DIN*

CAN Interface Wait for communication

from Commander

Note: ctrl registers can be written but are not active

*Channel activation is delayed by tPOR_DELAY when

entering after a Power On Reset

Reset

(transition state)

Reset of ctrl registers to

default value according to

Shadow Register setting

V3V3>V3V3_POR_H

WD failure

BUSMODE = GOSTBY = 0

BUSMODE = GOSTBY = 1

V3V3<V3V3_POR_L

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