ADF4377 datasheet(32/79 Pages) AD

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Data Sheet

ADF4377

APPLICATIONS INFORMATION

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Rev. 0 | 32 of 79

LOOP FILTER DESIGN

A stable loop filter design requires care in selecting the loop filter

components of the ADF4377. It is recommended to download and

install ADIsimPLL™ for loop filter design and simulation. ADIsimPLL

has an integrated tutorial for first time users and a help manual for

more complex topics. There are also several ADIsimPLL training

videos available on www.analog.com. After a loop filter has been

designed and simulated, it is recommended to verify the new loop

filter using the ADF4377 evaluation hardware.

A full loop filter design tutorial is beyond the scope of this data

sheet. However, some best practices are shown in the following

lists. ADIsimPLL aids in defining and simulating these parameters.

Any significant change to these items requires a new loop filter

design.

A stable loop filter must meet the following criteria:

►

Loop filter phase margin > 45°

►

Loop filter bandwidth <

fPFD÷10

The desired loop filter bandwidth is determined by the following

features of the ADF4377:

►

ICP

►

KVCO

►

PFD frequency

►

Reference input phase noise (see the Reference Phase Noise

section).

►

Trade-off between minimizing jitter or settling time (see the

Output Phase Noise Characteristics section and Equation 12,

respectively).

The VTUNE pin has an internal 30 pf capacitor to GND that must

be included in the loop filter design. ADIsimPLL takes this internal

capacitance into account automatically.

REFERENCE SOURCE CONSIDERATIONS

Reference Input Network

The reference input buffer of the ADF4377, shown in Figure 61,

provides a flexible interface to either differential or single-ended

frequency sources. Figure 80 to Figure 85 show recommended

interfaces for different reference signal types. All ZO signal traces

are 50 Ω transmission lines in Figure 80, Figure 81, Figure 82,

Figure 83, Figure 84, and Figure 85.

Figure 80. Single-Ended 50 Ω Source (VREF < 2.6 V p-p)

Figure 81. Single-Ended 50 Ω Source (VREF > 2.6 V p-p)

Figure 82. Single-Ended CMOS

Figure 83. Differential LVPECL

Figure 84. Differential LVDS

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