ADF4377 datasheet(23/79 Pages) AD

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Data Sheet

ADF4377

THEORY OF OPERATION

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Rev. 0 | 23 of 79

Table 8. FILT_REF Programming

FILT_REF

Sine Wave fREF

Square Wave fREF

≥20 MHz

All fREF

< 20 MHz

Not applicable

The BST_REF bit must be set based on the input signal level

to prevent the LNA reference input buffer from saturating. The

BST_REF programming is the same whether the input is a sine

wave or a square wave. See Table 9 for recommended settings and

the Applications Information section for programming examples.

Table 9. BST_REF Programming

BST_REF

Sine Wave VREF

≥ 1.6 V p-p

< 1.6 V p-p

Reference Peak Detector

A reference input peak detection circuit is provided on the REFP

and REFN inputs to detect the presence of a reference signal and

provides the REF_OK status flag available through serial port regis-

ter REG0049. The circuit has hysteresis to prevent the REF_OK

flag from chattering at the detection threshold.

The peak detector approximates an rms detector. Therefore, sine

and square wave inputs give different detection thresholds by a

factor of 4/π. See Table 10 for REF_OK detection values.

Table 10. REF_OK Status Output vs. Reference Input

REF_OK

Sine Wave VREF

Square Wave VREF

≥200 mV p-p

≥155 mV p-p

<160 mV p-p

<125 mV p-p

Reference Divider (R) and Doubler (D)

When the EN_RDBLR bit is set to 1, a frequency multiplier is used

to double the frequency seen at the PFD. When the EN_RDBLR bit

is set to 0, a 6-bit divider, R_DIV, is used to reduce the frequency

seen at the PFD. The reference divide ratio, R, may be set to any

integer from 1 to 63, inclusive of all the integer divide values. Use

the R_DIV bits found in REG0012 to directly program the R divide

ratio (see Figure 62 and Table 11). See the Output Frequency

section for the relationship between R, D, and the fREF, fPFD,

fVCO, and fOUT frequencies. The state of the DCLK_MODE bit is

determined by Table 17.

Figure 62. Reference Divider and Doubler

Table 11. EN_RDBLR and R_DIV Programming

EN_RDBLR

R_DIV

Not applicable

Not applicable 2

Not applicable

…

Not applicable

Reference Delay

A 7-bit delay, R_DEL, is used to increase the propagation delay

from the reference input pins to the clock outputs pins. Use the

R_DEL bits to directly program the reference delay (tRDEL) which

typically ranges from 0 ps to 127 ps in 1 ps steps (see Figure 63).

Figure 63. Typical Reference Delay Step Size vs. R_DEL Register Setting

INV_CLKOUT, N_DEL, and R_DEL can be used in conjunction to

align the multichip output to output skew to within ±0.5 ps. Figure

39 shows that the largest R_DEL settings may increase LNORM by

1 dB. INV_CLKOUT does not degrade performance and must be

used to adjust for multichip output to output skews greater than a

quarter of the 1/fOUT period, in lieu of a large N_DEL or R_DEL

value. As a result, the maximum tRDEL adjustment never has to

be more than a quarter of the 1/fOUT period. See the Aligning Multi-

ple ADF4377 Output Phases section for the relationship between

R_DEL, N_DEL, INV_CLKOUT, BLEED_I bit fields, Bits[9:0], and

BLEED_POL.

Phase/Frequency Detector (PFD)

The PFD, in conjunction with the charge pump, produces source

and sink current pulses proportional to the phase difference be-

tween the outputs of the reference divider or reference doubler and

feedback divider. This action provides the necessary feedback to

phase-lock the loop, forcing a phase alignment at the inputs of the

PFD. See Figure 64 for a simplified schematic of the PFD.

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