ADF4377 datasheet(22/79 Pages) AD

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Data Sheet

ADF4377

THEORY OF OPERATION

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OUTPUT FREQUENCY

When EN_RDBLR = 0

When the loop is locked, the frequency (fVCO ) (in Hz) produced at

the output of the VCO is determined by the reference frequency

(fREF) and the O, R, and N values given by Equation 1. Refer to

Table 11 and Table 18 for more information.

fVCO=fREF

×N×OR

(1)

In the following equation, the PFD frequency (fPFD) produced is

given by Equation 2.

fPFD

=fREFR

(2)

fVCO may be alternatively expressed as

fVCO=fPFD×N×O

(3)

The output frequency (fOUT) produced at the output of the output

divider is given by Equation 4.

fOUT=fVCOO

(4)

The output frequency resolution (fSTEP) produced by a unit change

in N is given by Equation 5.

fSTEP

=fPFD

(5)

When EN_RDBLR = 1

When the loop is locked, the frequency (fVCO ) (in Hz) produced at

the output of the VCO is determined by the reference frequency

(fREF) and the O, D, and N values given by Equation 6.

fVCO=fREF×D×N×O

(6)

When EN_RDBLR = 1, the PFD frequency (fPFD) produced is given

by Equation 7.

fPFD=fREF×D

(7)

Equation 3, Equation 4, and Equation 5 for fVCO, fOUT, and fSTEP

remain the same when EN_RDBLR = 1.

CIRCUIT DESCRIPTION

Reference Input Buffer

The reference frequency of the PLL is applied differentially on

the REFP pin and REFN pin. These high impedance inputs are

self-biased and must be ac-coupled with 1 µF capacitors (see

Figure 61 for a simplified schematic). Alternatively, the differential

inputs may be configured as a single ended input by applying the

reference frequency at REFP and bypassing REFN to GND with a 1

µF capacitor (see Figure 80).

Figure 61. Reference Input Stage

A high quality signal must be applied to the REFP and REFN inputs

because they provide the frequency reference to the entire PLL.

To achieve the in-band phase noise performance of the PLL, apply

a continuous waveform signal or a square wave with a slew rate

of at least 1000 V/µs. See the Reference Source Considerations

section for more information on reference input signal requirements

and interfacing.

When the REF_SEL bit is set to 0, the DMA buffer is selected. The

DMA is optimized for high slew rate signals, such as square waves

or higher frequency and higher amplitude sine waves. The DMA

has a controlled propagation delay from the reference input to clock

output, which eases time zero and over temperature multichip clock

alignment.

When the REF_SEL bit is set to 1, the LNA is selected. The LNA

is optimized for low slew rate signals, such as lower frequency or

lower amplitude sine waves.

The REF_SEL bit must be set correctly to optimize the in-band

phase noise performance and propagation delay. See Table 7,

Figure 37, and Equation 8 for recommended settings.

Table 7. REF_SEL Programming

REF_SEL Sine Wave Slew Rate (V/µs)

Square Wave

Optimized tPD

≥1500

Preferred

Yes

<1500

Not applicable

To calculate the slew rate of sine wave,

Slew Rate =2×π×f×V

(8)

where:

f = sine wave frequency

V = sine wave amplitude (in VPK)

The FILT_REF bit controls the low-pass filter of the reference input

LNA and must be set for sine wave signals based on fREF to limit

the wideband noise of the input reference signal. The FILT_REF bit

must be set correctly to reach the LNORM normalized in-band phase

noise floor. See Table 8 for recommended settings. Square wave

inputs must have FILT_REF set to 0.

ADF4377 Datasheet(PDF) 22 Page - Analog Devices

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