ADF4377 datasheet(40/79 Pages) AD

40 / 79 page

Data Sheet

ADF4377

APPLICATIONS INFORMATION

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Rev. 0 | 40 of 79

Table 38. ADF4377 Reference to Output Typical Performance Impact

Parameters

Reference and

Feedback Delay

Charge Pump

Bleed Current

Output Invert

Temperature

Coefficient

Minimal, Figure

18 and Figure 21

None, Figure 19

and Figure 22

None

LNORM

< 1 dB, Figure 39 < 1 dB, Figure 36 None

L1/f

< 1 dB, Figure 39 < 4 dB, Figure 36 None

Spurious

Minimal

fPFD ≥ 50 MHz:

minimal, fPFD < 50

MHz, contact ADI

Minimal

Lock Detector

None

See the Lock

Detector section

None

Figure 39 and Figure 37 show a general trend that an increasing

magnitude of R_DEL, N_DEL, or BLEED_I bit fields, Bits[9:0] caus-

es a small increase in LNORM and L1/f . Increases in LNORM and L1/f

result in clock jitter (see Figure 12 and Figure 15). Therefore, in the

most performance sensitive applications, identifying ways to mini-

mize the magnitude of the R_DEL, N_DEL, or BLEED_I bit fields,

Bits[9:0] values is desired. As an example, Figure 91 provides two

skew adjustment methods to minimize the skew in Figure 90. Meth-

od 1 only adjusts one of the reference to output delay adjustments

provided in Table 37. Method 1 results in an R_DEL, N_DEL, or

BLEED_I bit fields, Bits[9:0] maximum adjustment equal to half an

output cycle, or 1/(2 × fOUT). Method 2 minimizes the magnitude

of R_DEL, N_DEL, or BLEED_I bit fields, Bits[9:0] by utilizing the

output invert along with either R_DEL, N_DEL, or BLEED_I bit

fields, Bits[9:0] adjustments. When compared to Method 1, Method

2 results in a lower R_DEL, N_DEL, or BLEED_I bit fields, Bits[9:0]

maximum adjustment of a quarter cycle output cycle, or 1/(4 ×

fOUT). Method 2 is furthered described in Table 39.

Figure 91. Skew Adjustment Methods

Table 39. Method 2: Skew Adjustment

tSKEW_SYSTEM

Procedure

0<tSKEW_SYSTEM

≤14×fOUT

INV_CLKOUT = 0 and decrease tPD

1 4×fOUT <tSKEW_SYSTEM

≤24×fOUT

INV_CLKOUT = 1 and increase tPD

2 4×fOUT <tSKEW_SYSTEM

≤34×fOUT

INV_CLKOUT = 1 and decrease tPD

3 4×fOUT <tSKEW_SYSTEM

≤1fOUT

INV_CLKOUT = 0 and increase tPD

DESIGN EXAMPLE 2: JESD204B/C MULTICHIP

CLOCK AND SYSREF ALIGNMENT

This design Example 2 focuses on the system level approach

of ADI to minimize clock skew between converters, such as the

AD9213, that include a time to digital converter (TDC). For detailed

ADF4377 loop filter and register map design, follow the proce-

dure outlined in the Design and Programming Example 1: Single

ADF4377 section. Device specific programming and programming

details of the AD9213 and Stage 1 distribution IC are beyond the

scope of this example.

For this design example, assume the following goals:

►

Clock two AD9213 devices with two separate ADF4377 devices

►

Minimize clock skew at time zero

►

Provide procedure to measure and reduce clock skew errors

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