ADF4377 datasheet(27/79 Pages) AD

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Data Sheet

ADF4377

THEORY OF OPERATION

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Rev. 0 | 27 of 79

Figure 70. VCO Calibration Dividers

Figure 71. VCO Calibration Block

To perform a VCO calibration, set up several registers as outlined in

the following procedure:

1. Set register bits based on the RCLK column in Table 22.

2. Set DCLK_DIV1 = 1. Set CAL_CT_SEL, DCLK_DIV2, and

DCLK_MODE to the values in Table 17. Record fDIV_RCLK for

later use.

3. Calculate and set the minimum values for the

SYNTH_LOCK_TIMEOUT bit fields, Bits[14:0], the

VCO_ALC_TIMEOUT bit fields, Bits[14:0], and the

VCO_BAND_DIV bits. Typical automatic VCO calibration times

are 3 ms to 9 ms when minimum values are chosen for these

parameters. Larger values produce longer VCO calibration

times.

SYNTH_LOCK_TIMEOUT ≥Ceiling

200 μs×fDIV_RCLK

(13)

VCO_ALC_TIMEOUT≥Ceiling

50 μs×fDIV_RCLK

(14)

VCO_BAND_DIV≥Ceiling

15 μs×fDIV_RCLK

16×2DCLK_MODE

(15)

4. Ensure that the ADC_CLK_DIV bits are set so that the desired

ADC clock frequency is <400 kHz.

ADC_CLK_DIV >Ceiling

fDIV_RCLK

400 kHz −2

(16)

5. Set the N_INT bit fields, Bits[11:0], CLKOUT_DIV bits, R_DIV

bits, and EN_RDBLR bits by programming REG0010 last. Any

write to REG0010 starts the VCO automatic calibration.

6. This is an optional step. Monitor the register bits, ADC_BUSY

and FSM_BUSY. The calibration is finished when ADC_BUSY

transitions from high to low, followed by FSM_BUSY transition-

ing from high to low.

7. After the VCO calibration is complete, disable calibration clocks

to limit unwanted spurious content by setting EN_DRCLK =

EN_DNCLK = EN_ADC_CLK = 0.

8. This is an optional step. Read back the VCO_CORE,

VCO_BAND, and VCO_BIAS bits, and then record the read-

back values. These values can be used to bypass calibration

and manually program the M_VCO_CORE, M_VCO_BAND,

and M_VCO_BIAS bits for a given device and frequency, as

described in the Fast Power-Up and Initialization, Manually

Programmed VCO Calibration Settings (Optional) section.

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