ADF4377 datasheet(29/79 Pages) AD

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Data Sheet

ADF4377

THEORY OF OPERATION

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Rev. 0 | 29 of 79

INV_CLKOUT, N_DEL, and R_DEL can be used in conjunction to

align the multichip output to output skew to within ±0.5 ps. Figure

39 shows that the largest N_DEL settings may increase LNORM by

1 dB. INV_CLKOUT does not degrade performance and can be

used to adjust for multichip output to output skews greater than a

quarter of the 1/fOUT period, in lieu of a large N_DEL or R_DEL

value. As a result, the maximum tNDEL adjustment never has to

be more than a quarter of the 1/fOUT period. See the Aligning Multi-

ple ADF4377 Output Phases section for the relationship between

R_DEL, N_DEL, INV_CLKOUT, BLEED_I bit fields, Bits[9:0], and

BLEED_POL.

Clock Output Buffer

The low noise, differential output buffer in Figure 74 produces

a differential output voltage. The output amplitude level and com-

mon mode voltage is settable with the CLKOUT1_OP bits and

CLKOUT2_OP bits, according to Table 21. Each output can be

either ac-coupled or dc-coupled and terminated with 100 Ω, differ-

entially. If a single-ended output is desired, each side of the output

must be individually ac-coupled and terminated with 50 Ω (see

Figure 98).

Table 21. CLKOUT1_OP, CLKOUT2_OP Programming

CLKOUT1_OP,

CLKOUT2_OP

Differential

Amplitude (VOD)

Common-Mode Voltage

320 mVPEAK

VCLK − 1.2 × VOD

420 mVPEAK

VCLK − 1.2 × VOD

530 mVPEAK

VCLK − 1.2 × VOD

640 mVPEAK

VCLK − 1.2 × VOD

The outputs can be powered down individually by either setting

the ENCLK1 pin and ENCLK2 pin low or programming the

PD_CLKOUT1 and PD_CLKOUT2 bits to 1. The EN_CLK1 bit and

EN_CLK2 bit report the state of the ENCLK1 pin and ENCLK2 pin.

When powered down, the outputs source a common-mode voltage

around 2 V.

Figure 74. Simplified Clock Outputs

MUXOUT

Figure 75. MUXOUT

The state of the MUXOUT pin is determined by the serial port inter-

face (SPI) register bit field MUXOUT, which allows the user access

to various internal nodes. The MUXOUT pin and MUXOUT bits are

commonly used as an additional lock status output or to debug

PLL related issues during the hardware and software development

phase of a project. The CMOS_OV bit field determines if the logic

high level for the MUXOUT pin, LKDET pin, SDO pin, and SDIO pin

is 3.3 V or 1.8 V.

Temperature Sensor

Figure 76. Temperature Sensor

The temperature sensor is composed of an 8-bit ADC, which

measures the proportional to absolute temperature (PTAT) voltage

with respect to the reference (VREF) voltage of a bandgap. The

purpose of the temperature sensor is to measure changes in die

temperature, not the absolute junction temperature.

The maximum ADC clock frequency is 400 kHz. Equation 16

calculates the correct ADC_CLK_DIV value. The ADC clock may be

generated from either the SPI clock or the RCLK (see Figure 70).

Before an ADC measurement can occur, program the registers of

the ADF4377 as shown in Table 22.

Table 22. ADC Register Setup for SPI Clock and RCLK

Bits

RCLK1

SPI Clock

ADC_CLK_SEL

EN_DRCLK, EN_DNCLK

Not applicable

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