ADF4377 datasheet(44/79 Pages) AD

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Data Sheet

ADF4377

APPLICATIONS INFORMATION

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Rev. 0 | 44 of 79

Degradation of the SNR due to sample clock jitter only occurs if

the analog input signal is slewing. If the analog input signal is

stationary (dc), it does not matter when in time the sampling occurs.

Additionally, a faster slewing input signal yields a greater error

(more noise) than a slower slewing input signal.

Figure 94 demonstrates this effect. Note how much larger the error

term is with the fast slewing signal than with the slow slewing

signal. To maintain the SNR performance of the data converter,

digitization of high input frequency signals requires a clock with

much less jitter than applications with lower frequency input signals.

Figure 94. Fast and Slow Sine Wave Signals Sampled with a Jittery Clock

It is important to note that the frequency of the analog input signal

determines the jitter requirement of the sample clock. The actual

sample clock frequency does not matter. Many ADC applications

that under sample high frequency signals have especially challeng-

ing sample clock jitter requirements.

This information is useful for gaining an intuitive feel for the SNR

degradation due to sampling clock jitter. Quantitatively, the actual

sample clock jitter requirement for a given application is calculated

as follows:

tJTOTAL =10−SNRdB20

2×π×fSIG

(27)

where:

tJ(TOTAL) is the total RMS jitter in seconds

SNRdB is the SNR requirement in decibels

fSIG is the highest frequency signal to be digitized, expressed in Hz

The total jitter is the rms sum of the aperture jitter of the ADC and

the sample clock jitter, calculated as follows:

tJTOTAL = tJCLK2+tJADC2

(28)

Alternatively, for a given total jitter, the attainable SNR is calculated

as follows:

SNRdB=−20×log

2×π×fSIG×tJTOTAL (29)

These calculations assume a full-scale sine wave input signal. If

the input signal is a complex, modulated signal with a moderate

crest factor, the peak slew rate of the signal may be lower and the

sample clock jitter requirement may be relaxed.

These calculations are also theoretical. They assume a noiseless

ADC with infinite resolution. All realistic ADCs have both added

noise and a resolution limit. The limitations of the ADC must be

accounted for to prevent overspecifying the sampling clock.

Figure 95 plots the previous equations and provides a way to

estimate the sampling clock jitter requirement for a given input

signal or the expected SNR performance for a given sample clock

jitter.

Figure 95. SNR vs. Analog Input Frequency with Various Levels of Clock

Jitter

Measuring Clock Jitter Indirectly Using ADC

SNR

For some applications, integrating the phase noise of a clock

generator within a defined offset frequency range (for example, 12

kHz to 20 MHz) is sufficient to calculate the impact of the clock on

the overall system performance. In these situations, the rms jitter

can be calculated from a phase noise measurement.

However, other applications require knowledge of the phase noise

of the clock at frequency offsets that exceed the capabilities of

phase noise analyzers. This limitation makes it difficult to calculate

jitter from a phase noise measurement.

The rms jitter of an ADC clock source can be indirectly measured

by comparing a jitter dominated SNR measurement to a non-jitter

dominated SNR measurement. A jitter dominated SNR measure-

ment (SNRJITTER) is created by applying a low jitter, high frequency

full-scale sine wave to the ADC analog input. A non-jitter dominated

SNR measurement (SNRBASE) is created by applying a very low

amplitude (or low frequency) sine wave to the ADC analog input.

The total clock jitter (tJ(TOTAL)) can be calculated using Equation 30.

tJTOTAL

=1012×log1010−SNRJITTER10−10−SNRBASE10

2×π×fSIG

(30)

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