MEC1632 datasheet(70/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 70

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5.6.5

MEMORY BASE ADDRESS REGISTERS

Each Logical Device has a Memory Base Address Register (M-BAR). These M-BARs are located in blocks of Configu-

ration Registers in Logical Device 0Ch, in the AHB address range FF_33C0h through FF_33FFh. On every LPC bus

Memory access all Base Address Registers are checked in parallel and if any matches the LPC memory address the

MEC1632 claims the bus cycle.

Each M-BAR is 48 bits wide. The format of each M-BAR is summarized in Table 5-7, "Memory Base Address Register

Format". An LPC memory request is translated by the M-BAR into an 8-bit read or write transaction on the AHB bus.

The 32-bit LPC memory address is translated into a 24-bit AHB address

The Base Address Register Table is itself part of the AHB address space. It resides in the Configuration quadrant of

Logical Device Ch, the LPC Interface.

MASK

These bits are used to mask off address bits in the address match between an LPC memory address and the Host

Address field of the BARs, as described in Section 5.6.6, "Mapping LPC Memory Addresses".

FRAME

These 6 bits are used to specify a logical device frame number within a bus. This field is multiplied by 400h to provide

the frame address within the peripheral bus address. In the MEC1632 Frame values for frames corresponding to logical

devices that are not present on the MEC1632 are invalid.

VALID

If this bit is 1, the BAR is valid and will participate in LPC matches. If it is 0 this BAR is ignored.

HOST_ADDRESS

These 32 bits are used to match LPC memory addresses.

Note:

Software should that insure that no two BARs map the same LPC memory address. If two BARs do map

to the same address, the BAR_Conflict bit in the Host Bus Error Register is set when an LPC access tar-

geting the BARConflict address. An EC interrupt can be generated.

TABLE 5-7:

MEMORY BASE ADDRESS REGISTER FORMAT

BYTE5 BIT

D47

D46

D45

D44

D43

D42

D41

D40

BIT NAME

LPC Host Address Bits[31:24]

BYTE4 BIT

D39

D38

D37

D36

D35

D34

D33

D32

BIT NAME

LPC Host Address Bits[23:16]

BYTE3 BIT

D31

D30

D29

D28

D27

D26

D25

D24

BIT NAME

LPC Host Address Bits[15:08]

BYTE2 BIT

D23

D22

D21

D20

D19

D18

D17

D16

BIT NAME

LPC Host Address Bits[07:00]

BYTE1 BIT

D15

D14

D13

D12

D11

D10

BIT NAME

Valid

Reserved

Frame

BYTE0 BIT

D7D6D5D4D3D2D1D0

BIT NAME

Mask

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