MEC1632 datasheet(88/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 88

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The SIRQ data frame will now support IRQ2 from a logical device; previously IRQSER Period 3 was reserved for use

by the System Management Interrupt (nSMI). When using Period 3 for IRQ2, the user should mask off the MEC1632’s

SMI via the ESMI Mask Register. Likewise, when using Period 3 for nSMI, the user should not configure any logical

devices as using IRQ2.

IRQSER Period 14 is used to transfer IRQ13. Each Logical devices will have IRQ13 as a choice for their primary inter-

rupt.

Stop Cycle Control

Once all IRQ/Data Frames have completed, the host controller will terminate IRQSER activity by initiating a Stop Frame.

Only the host controller can initiate the Stop Frame. A Stop Frame is indicated when the IRQSER is low for two or three

clocks. If the Stop Frame’s low time is two clocks, then the next IRQSER cycle’s sampled mode is the Quiet mode; and

any IRQSER device may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame’s

pulse. If the Stop Frame’s low time is three clocks, then the next IRQSER cycle’s sampled mode is the continuous mode,

and only the host controller may initiate a Start Frame in the second clock or more after the rising edge of the Stop

Frame’s pulse.

Latency

Latency for IRQ/Data updates over the IRQSER bus in bridge-less systems with the minimum IRQ/Data Frames of 17

will range up to 96 clocks (3.84

S with a 25 MHz PCI Bus or 2.88s with a 33 MHz PCI Bus). If one or more PCI to PCI

Bridge is added to a system, the latency for IRQ/Data updates from the secondary or tertiary buses will be a few clocks

longer for synchronous buses, and approximately double for asynchronous buses.

EOI/ISR Read Latency

Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could cause an

EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a system fault. The host

interrupt controller is responsible for ensuring that these latency issues are mitigated. The recommended solution is to

delay EOIs and ISR Reads to the interrupt controller by the same amount as the IRQSER Cycle latency in order to

ensure that these events do not occur out of order.

AC/DC Specification Issue

All IRQSER agents must drive/sample IRQSER synchronously related to the rising edge of the PCI bus clock. The

IRQSER (SIRQ) pin uses the electrical specification of the PCI bus. Electrical parameters will follow the PCI Specifica-

tion Section 4, sustained tri-state.

Reset and Initialization

The IRQSER bus uses LRESET as its reset signal and follows the PCI bus reset mechanism. The IRQSER pin is tri-

stated by all agents while LRESET is active. With reset, IRQSER slaves and bridges are put into the (continuous) Idle

mode. The host controller is responsible for starting the initial IRQSER cycle to collect system’s IRQ/Data default values.

The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for subsequent IRQSER

cycles. It is the host controller’s responsibility to provide the default values to the 8259’s and other system logic before

the first IRQSER cycle is performed. For IRQSER system suspend, insertion, or removal application, the host controller

should be programmed into Continuous (IDLE) mode first. This is to ensure the IRQSER bus is in Idle state before the

system configuration changes.

8IRQ7

9IRQ8

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

TABLE 6-5:

IRQSER SAMPLING PERIODS (CONTINUED)

IRQSER Period

Signal Sampled

# of Clocks Past Start

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