MEC1632 datasheet(93/636 Pages) MICROCHIP

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DS00001592B-page 93

MEC1632

CLOCK_CONTROL

This field controls when the host interface will permit the internal ring oscillator to be shut down. The choices are as

follows:

0h:

The host interface will permit the ring oscillator to be shut down if the LPCPD# signal is asserted (sampled low)

1h:

The host interface will permit the ring oscillator to be shut down if the CLKRUN# signals “CLOCK STOP” and there

are no pending serial interrupt requests from devices associated with the MEC1632. The CLKRUN# signals

“CLOCK STOP” by CLKRUN# being high for 5 LPCCLK’s after the raising edge of CLKRUN#.

2h:

The host interface will permit the ring oscillator to be shut down after the completion of every LPC transaction. This

mode may cause an increase in the time to respond to LPC transactions if the ring oscillator is off when the LPC

transaction arrives at the MEC1632

3h:

The ring oscillator is not permitted to shut down as long as the host interface is active.

When the Activate bit in the Activate Register on page 89 is 0, the Host Interface will permit the ring oscillator to be shut

down and the Clock_Control Field is ignored. The Clock_Control Field only effects the Host Interface when the Activate

bit in the Activate Register is 1.

Although the Host Interface can permit the internal oscillator to shut down, it cannot turn the oscillator on in response

to an LPC transaction that occurs while the oscillator is off. In order to restart the oscillator in order to complete an LPC

transaction, EC firmware must enable a wake interrupt on the LPC LFRAME# input. See the Application Note in Section

17.3.5, "Wake Capable Interrupts" for details.

HAND SHAKE

This bit controls throughput of LPC transactions.

When this bit is a ‘0’. the MEC1632 only supports a 33MHz PCI Clock. When this bit is a ‘1’, the MEC1632 supports a

PCI Clock from 24MHz to 33MHz.

6.10.5

BAR INHIBIT REGISTER

BAR_INHIBIT[63:0]

When bit i of the BAR_Inhibit[63:0] field is asserted (‘1’), where i is the logical device number of one of the Host Logical

Devices in the MEC1632, the BAR for the associated device is disabled and its addresses will not be claimed on the

LPC bus, independent of the value of the Valid bit in the BAR. When bit i is not asserted (default), BAR activity for the

Logical Device is based on the Valid bit in the BAR.

All of the BAR_Inhibit[63:0] bits are R/W and have no affect on reserved logical device numbers. The Host Logical

Devices in the MEC1632 are shown in Table 4-2 in Section 4.3.2, "AHB Address Space," on page 59.

TABLE 6-12:

BAR INHIBIT REGISTER

HOST OFFSET

n/a

n/a HOST SIZE

EC ADDRESS

FF_3120h

64-bit EC SIZE

POWER

VTR

0000_0000_0000_0000h nSYS_RST DEFAULT

BUS

LPC SPB

BYTE3 BIT

D63

D62

D61

...

HOST TYPE

––

–

EC TYPE

R/W

BIT NAME

BAR_Inhibit[63:0]

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