MCT8317A datasheet(17/161 Pages) TI1

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8.3 Feature Description

8.3.1 Output Stage

The MCT8317A consists of an integrated 130-mΩ (high-side + low-side) NMOS FETs connected in a three-

phase bridge configuration. A doubler charge pump provides the proper gate-bias voltage to the high-side

NMOS FETs across a wide operating-voltage range in addition to providing 100% duty-cycle support. An internal

linear regulator provides the gate-bias voltage for the low-side MOSFETs.

8.3.2 Device Interface

MCT8317A supports I2C interface to provide end application design with adequate flexibility. MCT8317A allows

controlling the motor operation and system through BRAKE, DIR, EXT_CLK, EXT_WD and SPEED/WAKE pins.

MCT8317A also provides different signals for monitoring algorithm variables, speed, fault and phase current

feedback through DACOUT1, DACOUT2, FG, nFAULT, ALARM and SOX pins.

8.3.2.1 Interface - Control and Monitoring

Motor Control Signals

• When BRAKE pin is driven 'High', MCT8317A enters brake state. Low-side braking (see Low-Side

Braking) is implemented during this brake state. MCT8317A decreases output speed to value defined by

BRAKE_DUTY_THRESHOLD before entering brake state. As long as BRAKE is driven 'High', MCT8317A

stays in brake state. Brake pin input can be overwritten by configuring BRAKE_INPUT over the I2C interface.

• The DIR pin decides the direction of motor spin; when driven 'High', the sequence is OUT A → OUT C →

OUT B, and when driven 'Low' the sequence is OUT A → OUT B → OUT C. DIR pin input can be overwritten

by configuring DIR_INPUT over the I2C interface.

• SPEED/WAKE pin is used to control motor speed and wake up MCT8317A from sleep mode. SPEED pin can

be configured to accept PWM, frequency or analog input signals. It is used to enter and exit from sleep and

standby mode (see Table 8-2).

External Oscillator and Watchdog Signals (Optional)

• EXT_CLK pin may be used to provide an external clock reference (see External Clock Source ).

• EXT_WD pin may be used to provide an external watchdog signal (see External Watchdog).

Output Signals

• DACOUT1 outputs internal variable defined by address in register DACOUT1_VAR_ADDR, the output of

DACOUT1 is refreshed every PWM cycle (see DAC outputs).

• DACOUT2 outputs internal variable defined by address in register DACOUT2_VAR_ADDR, the output of

DACOUT2 is refreshed every PWM cycle (see DAC outputs).

• FG pin provides pulses which are proportional to motor speed (see FG Configuration).

• nFAULT pin provides fault status in device or motor operation.

• SOX pin provides the output of one of the current sense amplifiers.

8.3.2.2 I2C Interface

The MCT8317A supports an I2C serial communication interface that allows an external controller to send and

receive data. This I2C interface lets the external controller configure the EEPROM and read detailed fault and

motor state information. The I2C bus is a two-wire interface using the SCL and SDA pins which are described as

follows:

• The SCL pin is the clock signal input.

• The SDA pin is the data input and output.

8.3.3 AVDD Linear Voltage Regulator

A 3.3-V linear regulator is integrated into the MCT8317A and is available for use by external circuitry. The AVDD

regulator is used for powering up the internal circuitry of the device and additionally, this regulator can also

provide the supply voltage for an external low-power MCU or other circuitry supporting low current (up to 20 mA).

The AVDD nominal, no-load output voltage is 3.3-V.

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MCT8317A

SLLSFQ2 – JANUARY 2023

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