M95P16-IXMCSLASHEF datasheet(11/63 Pages) STMICROELECTRONICS

11 / 63 page

Device operation

4.1

Connecting to the SPI bus

All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial

data input (D) is sampled on the first rising edge of the Serial clock (C) after Chip select (S) goes low.

All output data bytes are shifted out of the device, most significant bit first. The Serial data output (on DQn pins) is

output on the first falling edge of the Serial clock (C) after eight bits of an instruction like Read from memory array

and Read Status register have been clocked into the device.

The Write protect (W) and Hold (HOLD) signals must be driven high or low, as appropriate.

Figure 4. Bus master and memory devices on the SPI bus

SPI Bus Master

SPI Interface with

CPOL,CPHA) =

(0,0 or (1,1)

SPI Memory

Device

SPI Memory

Device

SPI Memory

Device

Vss

Vcc

MOSI

MISO

CS3

CS2

CS1

Q,DQ1

Vcc

Vss

W,DQ2

D,DQ0

HOLD,DQ3

Q,DQ1

W,DQ2

D,DQ0

HOLD,DQ3

Vss

Q,DQ1

W,DQ2

D,DQ0

HOLD,DQ3

HOLD

Figure 4 shows an example of three memory devices connected to an SPI bus master. Only one memory device

is selected at a time, so only one memory drives the Serial data output (Q) line at a time. The other memory

devices are high-Z.

The pull-up resistor R (whose typical value is 100 kΩ) ensures that a device is not selected if the Bus master

leaves the S line in the high impedance state.

M95P16-I M95P16-E

Device operation

DS13710 - Rev 1

page 11/63

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