M95P16-IXMCSLASHEF datasheet(32/63 Pages) STMICROELECTRONICS

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6.13.4

Page erase (DBh)

The Page erase (PGER) instruction sets a page of 512 bytes within the device to the erased state of all 1s (FFh).

A Write enable instruction must first be executed before the device accepts the Page erase instruction (Status

code DBh. The instruction is completed by driving S high. The Page erase instruction sequence is shown in

Figure 23.

The S pin must be driven high after the eighth bit has been latched, or the instruction is not executed. After S is

driven high, the self-timed Page erase instruction starts, for a time duration of tPE (see Table 26. Programming

times). While the Page erase cycle is in progress, the Read Status register instruction can still be accessed to

check the status of the WIP bit. This bit is 1 during the Page erase cycle, and becomes 0 when the cycle finishes,

and the device is ready to accept further instructions. After the Page erase cycle is completed, the Write enable

latch (WEL) bit in the Status register is cleared to 0. The Page erase instruction is not executed if the addressed

page is protected by the block protection (BP2, BP1 and BP0) and TB bits. The status is reported with PAMAF

and ERF flags (see Table 9. Safety register format).

Figure 23. Page erase

A23

A22

A21

High impedance

PGER instruction

24-bit address

MS55409V1

6.14

Page program operations

6.14.1

Page program (0Ah)

The Page program (PGPR) instruction allows from one to 512 bytes of data, initially in the erased state (FFh),

to be programmed to 0. A Write enable instruction must be executed before the device accepts this instruction

(Status register bit WEL = 1).

The instruction is initiated by driving S low, then shifting the instruction code 0Ah, followed by a 24-bit address

(A23-A0) and at least one data byte into the D-DQ0 pin. The S pin must be held low for the whole length of the

instruction. The instruction is completed by driving S high. The sequence is shown in Figure 24.

Figure 24. Page program

4121 4122 4123 4124 4125 4126 4127 4128

A23 A22 A21

PGPR instruction

24-bit address

Data byte 1

Data bytes 2 to 511

Data byte 512

MS55413V1

S must be driven high after the eighth bit of the last byte has been latched, otherwise the instruction is rejected

and is not executed. After S is driven high, the self-timed Page program instruction starts for a time duration of

tpp (see Table 26. Programming times). While the Page program cycle is in progress, the Read Status register

instruction can still be accessed to check the status of the WIP bit, which is at 1 during the Page program cycle.

It becomes 0 when the cycle is finished and the device is ready to accept further instructions. When the Page

program cycle finishes, the Write enable latch (WEL) bit in the Status register is cleared to 0. The instruction is not

executed if the addressed page is protected by the block protection bits, and the status is reported with PAMAF,

ERF and PRF flags. See Table 9. Safety register format.

M95P16-I M95P16-E

Page program operations

DS13710 - Rev 1

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