M95P16-IXMCSLASHEF datasheet(36/63 Pages) STMICROELECTRONICS

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6.17

Fast read identification (8Bh)

The fast read identification (FRDID) instruction allows one or more data bytes in the two identification pages to be

sequentially read. With the addition of eight dummy clocks after the 24-bit address, it can operate at the highest

possible frequency fC (see Table 26. Programming times).

This instruction is initiated by driving the S pin low and shifting the instruction code 8Bh, followed first by a 24-bit

address (A23-A0) into the D-DQ0 pin, then by eight additional dummy clocks. The code and address bits are

latched on the rising edge of the C pin. After the eight dummy clocks are received, the data byte of the addressed

memory location is shifted out (MSB first) on the Q pin, on the falling edge of C. The address is automatically

incremented to the next higher address after each data byte is shifted out, thus enabling a continuous stream of

data. This means that the entire identification page (1024 bytes) can be accessed with a single instruction, as

long as the clock continues to cycle.

The address counter rolls over to 0 after the highest address of the second identification page is reached. The

instruction is completed by driving the S pin high. During the dummy clock cycles the data value on the D pin is

Don't care, and the Q pin is high-Z.

The FRDID instruction sequence is shown in Figure 27.

Figure 27. Fast read identification

A23 A22 A21

High impedance

4121 4122 4123 4124 4125 4126 4127 4128

High impedance

FRDID instruction

24-bit address

Data out 1

Data out 512

Dummy

MS69266V1

M95P16-I M95P16-E

Fast read identification (8Bh)

DS13710 - Rev 1

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