M95P16-IXMCSLASHEF datasheet(30/63 Pages) STMICROELECTRONICS

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6.13

Erase operations

Chip erase, Block erase, Sector erase and Page erase operations set the selected area bits to 1.

6.13.1

Chip erase (C7h)

The Chip erase (CHER) instruction sets all memory bits within the device to the erased state of 1 (FFh). A Write

enable instruction must be executed before the device accepts the Chip erase instruction (Status register bit

WEL must be 1). The instruction is initiated by driving the S pin low and shifting-in the instruction code C7h. The

instruction is completed by driving S high. The Chip erase instruction sequence is shown in Figure 20.

The S pin must be driven high after the eighth bit has been latched. If this is not done the Chip erase instruction

is not executed. After S is driven high, the self-timed Chip erase instruction starts, with a time duration of tCE (see

Table 26. Programming times). While the Chip erase cycle is in progress, the Read Status register instruction can

still be accessed to check the status of the WIP bit. The WIP bit is automatically set to 1 during the chip erase

cycle. It is reset to 0 when the device is ready to accept commands. After the Chip erase cycle has finished, the

Write enable latch (WEL) bit in the Status register is cleared to 0. The Chip erase instruction is not executed if any

addressed pages of the chip are protected by the block protection (BP2, BP1, and BP0) and TB bits. The status is

reported with PAMAF and ERF flags (see Table 9. Safety register format).

Figure 20. Chip erase

MS554891V1

CHER instruction

High impedance

6.13.2

Block erase (D8h)

The Block erase (BKER) instruction sets all memory bits within a specified block (64 Kbytes) to the erased state

of all 1s (FFh). A Write enable instruction must be executed before the device accepts the Block erase instruction

(the WEL Status register bit must be 1). The instruction is initiated by driving the S pin low and shifting-in the

instruction code D8h followed by a 24-bit block address (A23-A0). The instruction is completed by driving S high.

The Block erase instruction sequence is shown in Figure 21.

The S pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block

erase instruction is not executed. After S is driven high, the self-timed Block erase instruction starts, with a time

duration of tBE1 (see Table 26. Programming times). While the Block erase cycle is in progress, the Read Status

erase cycle. It transits to 0 when the cycle has finished and the device is ready to accept further instructions.

After the Block erase cycle is complete, the Write enable latch (WEL) bit in the Status register is cleared to 0. The

Block erase instruction is not executed if any addressed pages of the block are protected by the block protection

(BP2, BP1, and BP0) and TB bits. The status is reported with PAMAF and ERF flags (see Table 9. Safety register

format).

M95P16-I M95P16-E

Erase operations

DS13710 - Rev 1

page 30/63

M95P16-IXMC/EF Datasheet(PDF) 30 Page - STMicroelectronics