M95P16-IXMCSLASHEF datasheet(27/63 Pages) STMICROELECTRONICS

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6.9

Read data single output (03h)

The Read data single output (READ) instruction allows one or more data bytes to be sequentially read from the

memory. The instruction is initiated by driving the S pin low and then shifting the instruction code 03h, followed by

a 24-bit address (A23-A0) into the D pin. The code and address bits are latched on the rising edge of the C pin.

After the address is received, the data byte of the addressed memory location is shifted out (MSB first) on the Q

pin, on the falling edge of C. The address is automatically incremented to the next higher address after each data

byte is shifted out, allowing a continuous stream of data. This means that the whole memory can be accessed

with a single instruction, as long as the clock continues to cycle. The address counter rolls over to 0 after the

highest address is reached. The instruction is completed by driving S high.

The Read data single output instruction sequence is shown in Figure 16.

Figure 16. Read data single output

MS55469V1

Data Out 2

A23

A22

A21

High impedance

READ instruction

24-bit address

Data Out 1

6.10

Fast read single output with one dummy byte (0Bh)

The Fast read single output with one dummy byte (FREAD) instruction allows one or more data bytes to be

sequentially read from the memory. However, through the addition of eight dummy clocks after the 24-bit address,

it can operate at the highest possible frequency (see Table 27. AC characteristics - Other parameters).

The instruction is initiated by driving the S pin low and then shifting the instruction code 0Bh followed, first by a

24-bit address (A23-A0) into the D pin, then by eight additional dummy clock cycles.

The code and address bits are latched on the rising edge of the C pin. After the eight dummy clock cycles are

received, the data byte of the addressed memory location is shifted out (MSB first) on the Q pin, on the falling

edge of C. The address is automatically incremented to the next higher address after each byte of data is shifted

out, allowing a continuous stream of data. This means that the entire memory can be accessed with a single

instruction as long as the clock continues to cycle. The address counter rolls over to 0 after the highest address is

reached. The instruction is completed by driving S high.

During the dummy clock cycles the data value on the D pin is Don't care, and the Q pin is high-Z.

Figure 17. Fast read single output with one dummy byte

A23

A22

A21

High impedance

READ instruction

24-bit address

MS69255V1

Dummy clock cycles

Data Out 2

Data Out 1

High impedance

M95P16-I M95P16-E

Read data single output (03h)

DS13710 - Rev 1

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