M95P16-IXMCSLASHEF datasheet(17/63 Pages) STMICROELECTRONICS

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Status, Configurable, Safety, Volatile and SFDP registers

These registers provide:

•

the status of the availability and the setting of the memory array

•

the status of the output buffer strength

•

the status of the device after power up and ECC bit detection.

The Write Status/configuration register instructions can be used to configure the device write protection features.

5.1

Status register

The Status register can be read with the RDSR instruction in loop mode. The nonvolatile bits SRWD, TB, BP2,

BP1, and BP0 can be changed with the WRSR instruction when sending a data byte. The MSB (b7) is sent first.

Table 6. Status register format

SRWD

x(1)

BP2

BP1

BP0

WEL

WIP

1. x: Don't care bit.

Status register write protect (SRWD) bit

The nonvolatile Status register write disable (SRWD) bit is used in conjunction with the write protect (W) signal.

The Status register write disable (SRWD) bit and Write protect (W) signals enable the device to be put into

Hardware protected mode (when the Status register write disable (SRWD) bit is set to 1, and Write protect

(W) is driven low). In this mode, the nonvolatile bits of the Status register (SRWD, BP2, BP1, BP0 and TB)

become read-only bits, and the Write status register (WRSR) instruction is no longer accepted for execution. The

protection modes are described in Table 5. Protection modes.

Top / bottom protection (TB) bit

The nonvolatile Top/Bottom bit (TB) controls whether the block protection bits (BP2, BP1, BP0) protect from the

top (TB = 0) or from the bottom (TB = 1) of the array, as shown in Table 4. Protected area sizes. The factory

default setting is TB = 0. TB bit can be set with the Write Status register instruction, depending on the state of the

SRWD and WEL bits.

Block protection (BP2, BP1, BP0) bits

These are nonvolatile read/write bits in the Status register, which provide Write protection control and status.

All, none, or a portion of the memory array can be protected from Program and Erase instructions (see

Table 4. Protected area sizes). The factory default setting for the block protection bits is 0 (array unprotected).

The block protection bits can be set using the Write Status register instruction.

Write enable latch (WEL) bit

This is a read-only bit in the Status register, which is set to 1 after executing a Write enable instruction. The WEL

status bit is cleared to 0 when the device is Write disabled. A Write disable state occurs upon power-up, or after

correct completion of any of the following instructions: Write disable, Write, Page program, Sector erase, Block

erase, Chip erase, Write Status register.

Write in progress (WIP) bit

This is a read-only bit in the Status register, set to 1 when:

•

the device is executing a modify operation. During this time, the device ignores further instructions except

for the Read Status register. When the Program, Write, Erase or Write status/configuration register

instruction has completed, the WIP bit is cleared to 0, indicating that the device is ready for further

instructions.

•

the device is in power-up (see Table 14. Power-up/down conditions).

M95P16-I M95P16-E

Status, Configurable, Safety, Volatile and SFDP registers

DS13710 - Rev 1

page 17/63

M95P16-IXMC/EF Datasheet(PDF) 17 Page - STMicroelectronics

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