M95P16-IXMCSLASHEF datasheet(15/63 Pages) STMICROELECTRONICS

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4.12

Data protection and protocol control

The device features the following data protection mechanisms:

•

Power on reset and an internal timer (tPUW) can provide protection against inadvertent changes while the

power supply is outside the operating specification.

•

Before accepting the execution of the Program, Write and Erase and Write status register instructions, the

device checks whether the number of clock pulses comprising the instructions is a multiple of eight.

•

For any instruction to be accepted, and executed, Chip select (S) must be driven high after the rising edge

of the Serial clock (C) for the last bit of the instruction, and before the next rising edge of the Serial clock

(C).

•

All instructions that modify data must be preceded by a Write enable (WREN) instruction to set the write

enable latch (WEL) bit.

•

The block protection (BP2, BP1 and BP0) and TB bits in the Status register are used to configure part of

the memory as read-only.

•

The Write protect (W) signal is used to protect the block protection (BP2, BP1, BP0) and TB bits in the

Status register in conjunction with SRWD bit.

In addition to the low power consumption feature, the Deep power-down mode offers extra software protection: all

program and erase commands are ignored when the device is in this mode.

4.12.1

Memory protection scheme

The memory can be configured as read-only using the block protection (BP2, BP1, BP0) and TB bits, as shown in

Table 4. Refer to Section 5.1 Status register for more information on the BPn bits.

Table 4. Protected area sizes

BP2

BP1

BP0

Protected block(s)

Protected addresses

Protected size(1)

Protected portion

None

1F0000h – 1FFFFFh

64 KB

Upper 1/32

30 and 31

1E0000h – 1FFFFFh

128 KB

Upper 1/16

28 → 31

1C0000h – 1FFFFFh

256 KB

Upper 1/8

24 → 31

180000h – 1FFFFFh

512 KB

Upper 1/4

16 → 31

100000h – 1FFFFFh

1 MB

Upper 1/2

000000h – 00FFFFh

64 KB

Lower 1/32

0 and 1

000000h – 01FFFFh

128 KB

Lower 1/16

0 → 3

000000h – 03FFFFh

256 KB

Lower 1/8

0 → 7

000000h – 07FFFFh

512 KB

Lower 1/4

0 → 15

000000h – 0FFFFFh

1 MB

Lower 1/2

0 → 31

000000h – 1FFFFFh

2 MB

All

0 → 31

000000h – 1FFFFFh

2 MB

All

1. The device is ready to accept ERASE commands only if all block protect bits (BP2, BP1, BP0) are set to 0.

M95P16-I M95P16-E

Data protection and protocol control

DS13710 - Rev 1

page 15/63

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