STC12LE5604 datasheet(52/377 Pages) STC

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WDT_CONTR: Watch-Dog-Timer Control Register

SFR name

Address

bit

WDT_CONTR 0E1H

name WDT_FLAG -

EN_WDT CLR_WDT IDLE_WDT PS2 PS1 PS0

WDT_FLAG : WDT reset flag.

0 : This bit should be cleared by software.

1 : When WDT overflows, this bit is set by hardware to indicate a WDT reset happened.

EN_WDT

: Enable WDT bit. When set, WDT is started.

CLR_WDT : WDT clear bit. When set, WDT will recount. Hardware will automatically clear this bit.

IDLE_WDT : WDT IDLE mode bit. When set, WDT is enabled in IDLE mode. When clear, WDT is disabled in

IDLE.

PS2, PS1, PS0 : WDT Pre-scale value set bit.

Pre-scale value of Watchdog timer is shown as the bellowed table :

PS2

PS1

PS0

Pre-scale

WDT overflow Time @20MHz

39.3 mS

78.6 mS

157.3 mS

314.6 mS

629.1 mS

1.25 S

128

2.5 S

256

5 S

2.3.6 Watch-Dog-Timer

The watch dog timer in STC12C5620AD consists of an 8-bit pre-scaler timer and an 15-bit timer. The timer is

one-time enabled by setting EN_WDT(WDT_CONTR.5). Clearing EN_WDT can stop WDT counting. When

the WDT is enabled, software should always reset the timer by writing 1 to CLR_WDT bit before the WDT

overflows. If STC12C5620AD series MCU is out of control by any disturbance, that means the CPU can not run

the software normally, then WDT may miss the "writting 1 to CLR_WDT" and overflow will come. An overflow

of Watch-Dog-Timer will generate a internal reset.

1/256

1/128

1/64

1/32

1/16

1/8

1/4

1/2

8-bit prescalar

15-bit timer

WDT_FLAG

EN_WDT CLR_WDT IDLE_WDT PS2 PS1 PS0

SYSclk/12

IDL/PCON.0

WDT_CONTR

WDT Structure

WDT Reset

STC12LE5604 Datasheet(PDF) 52 Page - STCmicro Technology Co,.Ltd

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