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STC12LE5604 Datasheet(PDF) 93 Page - STCmicro Technology Co,.Ltd

Part # STC12LE5604
Description  Enhanced 8051 Central Processing Unit ,1T per machine cycle, faster 8~12 times than the rate of a standard 8051.
PDF  377 Pages
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Manufacturer  STC [STCmicro Technology Co,.Ltd]
Direct Link  http://www.stcmicro.com/
Logo STC - STCmicro Technology Co,.Ltd

STC12LE5604 Datasheet(HTML) 93 Page - STCmicro Technology Co,.Ltd

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ANL C, /bit
Bytes:
2
Cycles:
2
Encoding:
1 0 1 1
0 0 0 0
bit address
Operation:
ADD
(C)←(C)
←(C)
(C)
(bit)
CJNE <dest-byte>, <src-byte>, rel
Function:
Compare and Jump if Not Equal
Description:
CJNE compares the magnitudes of the first two operands, and branches if their values are not
equal. The branch destination is computed by adding the signed relative-displacement in the
last instruction byte to the PC, after incrementing the PC to the start of the next instruction.
The carry flag is set if the unsigned integer value of <dest-byte> is less than the unsigned
integer value of <src-byte>; otherwise, the carry is cleared. Neither operand is affected.
The first two operands allow four addressing mode combinations: the Accumulator may
be compared with any directly addressed byte or immediate data, and any indirect RAM
location or working register can be compared with an immediate constant.
Example:
The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence
CJNE
R7,#60H, NOT-EQ
;
. . .
. . . . . .
; R7 = 60H.
NOT_EQ:
JC
REQ_LOW
; IF R7 < 60H.
;
. . .
. . . . .
; R7 > 60H.
sets the carry flag and branches to the instruction at label NOT-EQ. By testing the carry flag,
this instruction determines whether R7 is greater or less than 60H.
If the data being presented to Port 1 is also 34H, then the instruction,
WAIT: CJNE A,P1,WAIT
clears the carry flag and continues with the next instruction in sequence, since the
Accumulator does equal the data read from P1. (If some other value was being input on Pl,
the program will loop at this point until the P1 data changes to 34H.)
CJNE A,direct,rel
Bytes:
3
Cycles:
2
Encoding:
1 0 1 1
0 1 0 1
direct address
rel. address
Operation:
(PC) ← (PC) + 3
← (PC) + 3
(PC) + 3
IF (A) < > (direct)
THEN
(PC) ← (PC) +
← (PC) +
(PC) + relative offset
IF (A) < (direct)
THEN
(C) ← 1
← 11
ELSE
(C) ← 0
← 00
93



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