7.4.4 Fail-Safe Input (TLV3012-EP Only)

This section does NOT apply to the open drain output TLV3011-EP.

The TLV3012-EP inputs are Fail-Safe up to 5.5V independent of V+ voltage. Fail-Safe is defined as maintaining

the same high input impedance when V+ is unpowered or within the recommended operating ranges.

The Fail-Safe inputs can be any value between 0 V and 5.5 V, even while V+ is zero or ramping up or down.

This feature avoids power sequencing issues as long as the input voltage range and supply voltage are within

the specified ranges.

This is possible since the inputs are not clamped to V+ and the input current maintains its value even when a

higher voltage is applied to the inputs.

As long as one of the input pins remains within the valid input range, and the supply voltage is valid and not in

POR, the output state will be correct. The specified input voltage range is -0.2 V to (V+) + 0.2 V.

The following is a summary of the TLV3012-EP device input voltage excursions and their outcomes:

1. When both IN- and IN+ are within the specified input voltage range:

a. If IN- is higher than IN+ and the offset voltage, the output is low.

b. If IN- is lower than IN+ and the offset voltage, the output is high.

2. When IN- is higher than the specified input voltage range and IN+ is within the specified voltage range, the

output is low.

3. When IN+ is higher than the specified input voltage range and IN- is within the specified input voltage range,

the output is high

4. When IN- and IN+ are both outside the specified input voltage range, the output state is indeterminate

(random). Do not operate in this region.

Because the inputs do not have upper ESD diode clamps to V+, input voltages must be externally clamped to

below 5.5 V if the source could possibly exceed 5.5 V. A current limiting resistor in series with the input is also

recommend in case of input transients.

7.4.5 Power-On Reset (POR) (TLV3012-EP Only)

This section does NOT apply to the open-drain output TLV3011-EP.

The TLV3012-EP has an internal Power-on-Reset (POR) circuit for known start-up or power-down conditions.

While the power supply (V+) is ramping up or ramping down, the POR circuitry will be activated for up to 1.9ms

after the minimum supply voltage threshold is crossed, or immediately when the supply voltage drops below

minimum supply. When the supply voltage is equal to or greater than the minimum supply voltage, and after the

delay period, the comparator output reflects the state of the differential input (VID). This delay is long enough to

allow the reference output to stabilize with up to a 10nF capacitive load.

During the POR period (ton), the outputs will be low (sinking)

Power On Reset Time (tON)

VOH / 2

VOL

OUT

VS

+1.5V

0V

Figure 7-1. Power-On Reset Example Timing Diagram for TLV3012-EP

www.ti.com

TLV3011-EP, TLV3012-EP

SGLS349A – OCTOBER 2006 – REVISED MAY 2023

Copyright © 2023 Texas Instruments Incorporated

Submit Document Feedback

19

Product Folder Links: TLV3011-EP TLV3012-EP