LXT386LE datasheet(45/78 Pages) INTEL

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QUAD T1/E1/J1 Transceiver — LXT386

Datasheet

5.0

JTAG Boundary Scan

5.1

Overview

The LXT386 supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy

access to the interface pins for board testing purposes.

In addition to the traditional IEE1149.1 digital boundary scan capabilities, the LXT386 also

includes analog test port capabilities. This feature provides access to the TIP and RING signals in

each channel (transmit and receive). This way, the signal path integrity across the primary winding

of each coupling transformer can be tested.

5.2

Architecture

Figure 15 represents the LXT386 basic JTAG architecture. The LXT386 JTAG architecture

includes a TAP Test Access Port Controller, data registers and an instruction register. The

following paragraphs describe these blocks in detail.

5.3

TAP Controller

The TAP controller is a 16 state synchronous state machine controlled by the TMS input and

clocked by TCK ( Figure 16).The TAP controls whether the LXT386 is in reset mode, receiving an

instruction, receiving data, transmitting data or in an idle state. Table 30 describes in detail each of

the states represented in Figure 16.

Figure 15. LXT386 JTAG Architecture

MUX

TDO

TAP

Controller

TCK

TMS

TRST

TDI

Boundry Scan Data Register

BSR

Analog Port Scan Register

ASR

Device Identification Register

IDR

Bypass Register

BYR

Instruction Register

LXT386LE Datasheet(PDF) 45 Page - Intel Corporation