56F8322 datasheet(48/136 Pages) FREESCALE

48 / 136 page

56F8322 Techncial Data, Rev. 16

Freescale Semiconductor

Preliminary

Table 4-23 GPIOC Registers Address Map

(GPIOC_BASE = $00F310)

Address Offset

Reset Value

GPIOC_PUR

Pull-up Enable Register

0 x 007C

GPIOC_DR

Data Register

0 x 0000

GPIOC_DDR

Data Direction Register

0 x 0000

GPIOC_PER

Peripheral Enable Register

0 x 007F

GPIOC_IAR

Interrupt Assert Register

0 x 0000

GPIOC_IENR

Interrupt Enable Register

0 x 0000

GPIOC_IPOLR

Interrupt Polarity Register

0 x 0000

GPIOC_IPR

Interrupt Pending Register

0 x 0000

GPIOC_IESR

Interrupt Edge-Sensitive Register

0 x 0000

GPIOC_PPMODE

Push-Pull Mode Register

0 x 007F

GPIOC_RAWDATA

Raw Data Input Register

—

Table 4-24 System Integration Module Registers Address Map

(SIM_BASE = $00 F350)

Address Offset

SIM_CONTROL

Control Register

SIM_RSTSTS

Reset Status Register

SIM_SCR0

Software Control Register 0

SIM_SCR1

Software Control Register 1

SIM_SCR2

Software Control Register 2

SIM_SCR3

Software Control Register 3

SIM_MSH_ID

Most Significant Half JTAG ID

SIM_LSH_ID

Least Significant Half JTAG ID

SIM_PUDR

Pull-up Disable Register

Reserved

SIM_CLKOSR

Clock Out Select Register

SIM_GPS

GPIO Peripheral Select Register

SIM_PCE

Peripheral Clock Enable Register

SIM_ISALH

I/O Short Address Location High Register

SIM_ISALL

I/O Short Address Location Low Register

Table 4-25 Power Supervisor Registers Address Map

(LVI_BASE = $00 F360)

Address Offset

LVI_CONTROL

Control Register

LVI_STATUS

Status Register

56F8322 Datasheet(PDF) 48 Page - Freescale Semiconductor, Inc

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