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56F8322 Datasheet(PDF) 74 Page - Freescale Semiconductor, Inc |
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56F8322 Datasheet(HTML) 74 Page - Freescale Semiconductor, Inc |
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74 / 136 page ![]() 56F8322 Techncial Data, Rev. 16 74 Freescale Semiconductor Preliminary 5.6.14.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0 The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register. 5.6.15 Fast Interrupt 1 Match Register (FIM1) Figure 5-17 Fast Interrupt 1 Match Register (FIM1) 5.6.15.1 Reserved—Bits 15–7 This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing. 5.6.15.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 6–0 This value determines which IRQ will be a Fast Interrupt 1. Fast interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first; see Section 5.3.3 for details. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table 4-3. 5.6.16 Fast Interrupt 1 Vector Address Low Register (FIVAL1) Figure 5-18 Fast Interrupt 1 Vector Address Low Register (FIVAL1) 5.6.16.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0 The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register. 5.6.17 Fast Interrupt 1 Vector Address High Register (FIVAH1) Figure 5-19 Fast Interrupt 1 Vector Address High Register (FIVAH1) Base + $E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 1 Write RESET 00000 0000000 0000 Base + $F 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read FAST INTERRUPT 1 VECTOR ADDRESS LOW Write RESET 00000 0000000 0000 Base + $10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 1 VECTOR ADDRESS HIGH Write RESET 00000 0000000 0000 |
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