56F8322 datasheet(77/136 Pages) FREESCALE

77 / 136 page

56F8322 Technical Data, Rev. 16

Freescale Semiconductor

Preliminary

5.6.23

IRQ Pending 5 Register (IRQP5)

Figure 5-25 IRQ Pending Register 5 (IRQP5)

5.6.23.1

Reserved—Bits 96–82

This bit field is reserved or not implemented. The bits are read as 1 and cannot be modified by writing.

5.6.23.2

IRQ Pending (PENDING)—Bit 81

This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2

through 81.

•

0 = IRQ pending for this vector number

•

1 = No IRQ pending for this vector number

5.6.24

Reserved—Base + 17

5.6.25

Reserved—Base + 18

5.6.26

Reserved—Base + 19

5.6.27

Reserved—Base + 1A

5.6.28

Reserved—Base + 1B

5.6.29

Reserved—Base + 1C

5.6.30

ITCN Control Register (ICTL)

Figure 5-26 ITCN Control Register (ICTL)

5.6.30.1

Interrupt (INT)—Bit 15

This read-only bit reflects the state of the interrupt to the 56800E core.

•

0 = No interrupt is being sent to the 56800E core

•

1 = An interrupt is being sent to the 56800E core

Base + $16

Read

PEND-

ING

[81]

Write

RESET

111

Base + $1D

Read

INT

IPIC

VAB

INT_DIS

IRQA STATE

IRQA EDG

Write

RESET

000

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