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56F8322 Datasheet(PDF) 92 Page - Freescale Semiconductor, Inc |
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56F8322 Datasheet(HTML) 92 Page - Freescale Semiconductor, Inc |
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92 / 136 page ![]() 56F8322 Techncial Data, Rev. 16 92 Freescale Semiconductor Preliminary Figure 6-13 I/O Short Address Determination With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register to its previous contents prior to returning from interrupt. Note: The default value of this register set points to the EOnCE registers. Note: The pipeline delay between setting this register set and using short I/O addressing with the new value is five cycles. Figure 6-14 I/O Short Address Location High Register (SIM_ISALH) 6.5.10.1 Input/Output Short Address Low (ISAL[23:22])—Bit 1–0 This field represents the upper two address bits of the “hard coded” I/O short address. Figure 6-15 I/O Short Address Location Low Register (SIM_ISALL) Base + $D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ISAL[23:22] Write RESET 11111 1 1 1 1 1 1 1 1 1 1 1 Base + $E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read ISAL[21:6] Write RESET 11111 1 1 1 1 1 1 1 1 1 1 1 Instruction Portion “Hard Coded” Address Portion 6 Bits from I/O Short Address Mode Instruction 16 Bits from SIM_ISALL Register 2 bits from SIM_ISALH Register Full 24-Bit for Short I/O Address |
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