56F8322 datasheet(73/136 Pages) FREESCALE

73 / 136 page

56F8322 Technical Data, Rev. 16

Freescale Semiconductor

Preliminary

5.6.12

Fast Interrupt 0 Match Register (FIM0)

Figure 5-14 Fast Interrupt 0 Match Register (FIM0)

5.6.12.1

Reserved—Bits 15–7

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.12.2

Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 6–0

This value determines which IRQ will be a Fast Interrupt 0. Fast interrupts vector directly to a service

routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table

first; see Section 5.3.3 for details. IRQs used as fast interrupts must be set to priority level 2. Unexpected

results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become

the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being

declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector

number of each IRQ, refer to Table 4-3.

5.6.13

Fast Interrupt 0 Vector Address Low Register (FIVAL0)

Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0)

5.6.13.1

Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0

The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0

to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.

5.6.14

Fast Interrupt 0 Vector Address High Register (FIVAH0)

Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0)

5.6.14.1

Reserved—Bits 15–5

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

Base + $B

Read

FAST INTERRUPT 0

Write

RESET

00000

0000000

0000

Base + $C

Read

FAST INTERRUPT 0 VECTOR ADDRESS LOW

Write

RESET

00000

0000000

0000

Base + $D

Read

FAST INTERRUPT 0 VECTOR

ADDRESS HIGH

Write

RESET

00000

0000000

0000

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