56F8322 datasheet(16/136 Pages) FREESCALE

16 / 136 page

56F8322 Techncial Data, Rev. 16

Freescale Semiconductor

Preliminary

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F8322 and 56F8122 devices are organized into functional groups,

as detailed in Table 2-1 and as illustrated in Figure 2-1 and Figure 2-2. In Table 2-2, each table row

describes the signal or signals present on a pin.

Note: See Table 1-1 for 56F8122 functional differences.

Table 2-1 Functional Group Pin Allocations

Functional Group

Number of Pins in Package

56F8322

56F8122

Power (VDD or VDDA)

Ground (VSS or VSSA)

Supply Capacitors & VPP

1. The VPP input shares the IRQA input

PLL and Clock

Interrupt and Program Control

Pulse Width Modulator (PWM) Ports2

2. Pins in this section can function as SPI #1 and GPIO.

7—

Serial Peripheral Interface (SPI) Port 03

3. Pins in this section can function as SCI #1 and GPIO.

Quadrature Decoder Port 04

4. Alternately, can function as Quad Timer A pins or GPIO.

4—

CAN Ports

2—

Analog to Digital Converter (ADC) Ports

Timer Module Port C5

5. Pins can function as SCI #0 and GPIO.

Timer Module Port A

—4

JTAG/Enhanced On-Chip Emulation (EOnCE)

Temperature Sense6

6. Tied internally to ANA7

0—

Dedicated GPIO

—5

56F8322 Datasheet(PDF) 16 Page - Freescale Semiconductor, Inc