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SAA7780 Datasheet(PDF) 40 Page - NXP Semiconductors |
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SAA7780 Datasheet(HTML) 40 Page - NXP Semiconductors |
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40 / 70 page ![]() ThunderBird Q3D PCI Audio SAA7780 Accelerator Philips Semiconductors Product Specification 1999 Sep 30 40 MIDI Base Address - MDBASE (RW/RO) D23 D22 D21 D20 D19 D18 D17 D16 SBBASE[23:16] POR Value 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 SBBASE[15:8] POR Value 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 SBBASE[7:4] R R R IO POR Value 0 0 0 0 0 0 0 1 Bit Name R/W Function 31:4 SBBASE RW Sound Blaster programmable base address. The address should be on a 16 byte boundary. For reference, the Sound Blaster legacy base addresses are 220h and 240h. Note that accesses from the AdLib base address are mapped into a subset of the SoundBlaster registers. 3:1 R RO Reserved. These bits are reserved and always return zeros for plug and play. 0 IO RO I/O flag. This read only bit indicates that this is an I/O range. PCI CFG 0 D31 D30 D29 D28 D27 D26 D25 D24 Offset 18h MDBASE[31:24] POR Value 0 0 0 0 0 0 0 0 D23 D22 D21 D20 D19 D18 D17 D16 MDBASE[23:16] POR Value 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 MDBASE[15:8] POR Value 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 |
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