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SAA7780 Datasheet(PDF) 64 Page - NXP Semiconductors |
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SAA7780 Datasheet(HTML) 64 Page - NXP Semiconductors |
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64 / 70 page ![]() ThunderBird Q3D PCI Audio SAA7780 Accelerator Philips Semiconductors Product Specification 1999 Sep 30 64 FIGURE 6 Multimedia Timer Block Diagram Multimedia Timer Register Definition There are five registers that control the multimedia timer. These registers are the timer control register, timer status, and timer count registers. The timer control register resides in PCI configuration space. The remainder of the timer registers are in I/O space. Multimedia Timer PCI Configuration Registers Multimedia Timer Configuration Register 0 - TIMRCFG0 (RW/RO) PCI CFG 0 D7 D6 D5 D4 D3 D2 D1 D0 Offset 64h R R R R R FSTCLK TMRRST R POR Value 0 0 0 0 0 0 0 0 Bit Name R/W Function 7:3 R RO Reserved. These bits return zeros. PS BUS CLOCK DIVIDE LOGIC OSC CTL INTERNAL PS BUS INTERFACE INTERRUPT GENERATION LOGIC 20 BIT - 1uS RESOLUTION UP COUNTER CTL COUNT INTR COUNTER CLOCK |
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