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SAA7780 Datasheet(PDF) 31 Page - NXP Semiconductors

Part # SAA7780
Description  ThunderBird Q3D PCI Audio Accelerator
PDF  70 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SAA7780 Datasheet(HTML) 31 Page - NXP Semiconductors

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ThunderBird Q3D PCI Audio
SAA7780
Accelerator
Philips Semiconductors
Product Specification
1999 Sep 30
31
These bits correspond to Function 0, Subsystem ID (offset 2Eh) bits 2, 1, and 0, respectively. The Vendor should
choose and ID that corresponds to the peripherals present and program the EEPROM accordingly.
PCI Data Path
The PCI datapath provides the flip flop and multiplexers required to convert the external PCI interface address, data,
command and byte enables busses to the internal PM and PS busses.
PCI Configuration Registers
Since the SAA7780 is a multi-function device, there are three configuration headers. They are defined as the audio
configuration header as function 0, the joystick configuration header as function 1, and the UART configuration header
defined as function 2. Each configuration space is divided up into two groups, the registers that stay with the PCI
interface and the registers that do not. This section will describe the PCI configuration registers that bunk with the PCI
interface. These registers include the PCI standard configuration header registers and the base address registers for
various blocks in the SAA7780 chip.
To be more specific, the registers in the offset config space from 00h - 3Fh are the predefined PCI configuration
header. All three PCI configuration header registers will reside with the PCI interface. The remainder of the registers
are function specific and can be found in the block section itself.
The following sections will detail each of the configuration header spaces for each of the SAA7780 functions: audio,
joystick and UART.
PCI Configuration Space 0
The following table is a summary of all the PCI configuration space registers. The registers that are block-mates with
the PCI interface (offset 00h - 44h) will be detailed following the PCI configuration space table. The remainder of the
003h
12
013h
12
023h
12
033h
12
043h
12
053h
12
004h
11
014h
11
024h
11
034h
11
044h
11
054h
11
005h
10
015h
10
025h
10
035h
10
045h
10
055h
10
006h
9
016h
9
026h
9
036h
9
046h
9
056h
9
007h
8
017h
8
027h
8
037h
8
047h
8
057h
8
008h
7
018h
7
028h
7
038h
7
048h
7
058h
7
009h
6
019h
6
029h
6
039h
6
049h
6
059h
6
00Ah
5
01Ah
5
02Ah
5
03Ah
5
04Ah
5
05Ah
5
00Bh
4
01Bh
4
02Bh
4
03Bh
4
04Bh
4
05Bh
4
00Ch
3
01Ch
3
02Ch
3
03Ch
3
04Ch
3
05Ch
3
00Dh
2
01Dh
2
02Dh
2
03Dh
2
04Dh
2
05Dh
2
00Eh
1
01Eh
1
02Eh
1
03Eh
1
04Eh
1
05Eh
1
00Fh
0
01Fh
0
02Fh
0
03Fh
0
04Fh
0
05Fh
0
Function 0 - Audio Subsystem
Function 1 - Joystick
Function 2 - 16650 Modem UART
Subsystem
Vendor ID - Offset
2Ch
Subsystem ID -
Offset 2Eh
Subsystem
Vendor ID - Offset
2Ch
Subsystem ID -
Offset 2Eh
Subsystem
Vendor ID - Offset
2Ch
Subsystem ID -
Offset 2Eh
EEPROM
Bit #
Reg
Bit #
EEPROM
Bit #
Reg
Bit #
EEPROM
Bit #
Reg
Bit #
EEPROM
Bit #
Reg
Bit #
EEPROM
Bit #
Reg
Bit #
EEPROM
Bit #
Reg
Bit #



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