AM79C940JCSLASHW datasheet(30/144 Pages) AMD

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Am79C940

FUNCTIONAL DESCRIPTION

The Media Access Controller for Ethernet (MACE) chip

embodies the Media Access Control (MAC) and Phys-

ical Signaling (PLS) sub-layers of the 802.3 Standard.

The MACE device provides the IEEE defined Attach-

ment Unit Interface (AUI) for coupling to remote Media

Attachment Units (MAUs) or on-board transceivers.

The MACE device also provides a Digital Attachment

I n te r f ace ( D AI) , by-p a ssing t he d i f f er e n tia l

AUI interface.

The system interface provides a fundamental data

conduit to and from an 802.3 network. The MACE de-

vice in conjunction with a user defined DMA engine,

provides an 802.3 interface tailored to a specific

application.

In addition, the MACE device can be combined with

simila rly architected periphe ral d evices an d a

multi-channel DMA controller, thereby providing the

system with access to multiple peripheral devices with

a single master interface to memory.

Network Interfaces

The MACE device can be connected to an 802.3 net-

work using any one of the AUI, 10 BASE-T, DAI and

GPSI network interfaces. The Attachment Unit Inter-

face (AUI) provides an IEEE compliant differential in-

terface to a remote MAU or an on-board transceiver.

An integrated 10BASE-T MAU provides a direct inter-

face for twisted pair Ethernet networks. The DAI port

can connect to local transceiver devices for 10BASE2,

10BASE-T or 10BASE-F connections. A General Pur-

pose Serial Interface (GPSI) is supported, which effec-

tively bypasses the integrated Manchester encoder/

decoder, and allows direct access to/from the integral

802.3 Media Access Controller (MAC) to provide sup-

port for external encoding/decoding schemes. The in-

terface in use is determined by the PORTSEL [1-0] bits

in the PLS Configuration Control register.

The EADI port does not provide network connectivity,

but allows an optional external circuit to assist in

receive packet accept/reject.

System Interface

The MACE device is a slave register based peripheral.

All transfers to and from the device, including data, are

performed using simple memory or I/O read and write

commands. Access to all registers, including the Trans-

mit and Receive FIFOs, are performed with identical

read or write timing. All information on the system inter-

face is synchronous to the system clock (SCLK), which

allows simple external logic to be designed to

interrogate the device status and control the network

data flow.

The Receive and Transmit FIFOs can be read or writ-

ten by driving the appropriate address lines and assert-

ing CS and R/W. A n alter nati ve F I FO ac cess

mechanism allows the use of the FDS and the R/W

lines, ignoring the address lines (ADD4-0). The state of

the R/W line in conjunction with the FDS input deter-

mines whether the Receive FIFO is read (R/W high) or

the Transmit FIFO written (R/W low). The MACE de-

vice system interface permits interleaved transmit and

receive bus transfers, allowing the Transmit FIFO to be

filled (primed) while a frame is being received from the

network and/or read from the Receive FIFO.

In receive operation, the MACE device asserts Receive

Data Transfer Request (RDTREQ) when the FIFO con-

tains adequate data. For the first indication of a new

receive frame, 64 bytes must be received, assuming

normal operation. Once the initial 64 byte threshold has

been reached, RDTREQ assertion and de-assertion is

dependent on the programming of the Receive FIFO

Watermark (RCVFW bits in the BIU Configuration Con-

trol register). The RDTREQ can be programmed to

activate when there are 16, 32 or 64 bytes of data avail-

able in the Receive FIFO. Enable Receive (ENRCV bit

in MAC Configuration Control register) must be set to

assert RDTREQ. If the Runt Packet Accept feature is

invoked (RPA bit in User Test Register), RDTREQ will

be asserted for receive frames of less than 64 bytes on

the basis of internal and/or external address match

only. When RPA is set, RDTREQ will be asserted when

the entire frame has been received or when the initial

64 byte threshold has been exceeded. See the FIFO

Sub-Systems section for further details.

Note that the Receive FIFO may not contain 64 data

bytes at the time RDTREQ is asserted, if the automatic

pad stripping feature has been enabled (ASTRP RCV

bit in the Receive Frame Control register) and a mini-

mum length packet with pad is received. The MACE

device will check for the minimum received length from

the network, strip the pad characters, and pass only the

data frame through the Receive FIFO.

If the Low Latency Receive feature is enabled (LLRCV

bit set in Receive Frame Control Register), RDTREQ

will be asserted once a low watermark threshold has

been reached (12 bytes plus some additional synchro-

nization time). Note that the system interface will there-

fore be exposed to potential disruption of the receive

frame due to a network condition (see the FIFO

Sub-System description for additional details).

In transmit operation, the MACE device asserts Trans-

mit Data Transfer Request (TDTREQ) dependent on

the programming of the Transmit FIFO Watermark

(XMTFW bits in the BIU Configuration Control register).

TDTREQ will be permanently asserted when the

Transmit FIFO is empty. The TDTREQ can be pro-

grammed to activate when there are 16, 32 or 64 bytes

of space available in the Transmit FIFO. Enable Trans-

mit (ENXMT bit in MAC Configuration Control register)

must be set to assert TDTREQ. Write cycles to the

AM79C940JC/W Datasheet(PDF) 30 Page - Advanced Micro Devices

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