AM79C940JCSLASHW datasheet(41/144 Pages) AMD

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Am79C940

input rise and fall time. SRDCLK strobes the data

receiver output at 1/4 bit time to determine the value of

the Manchester bit and clocks the data out on SRD on

the following SRDCLK. The data receiver also gener-

ates the signal used for phase detector comparison to

the internal SIA voltage controlled oscillator (VCO).

Differential Input Terminations

The differential input for the Manchester data (DI

±) is

externally terminated by two 40.2 ohm

±1% resistors

and one optional common-mode bypass capacitor, as

shown in the Differential Input Termination diagram

below. The differential input impedance, ZIDF, and the

common-mode input impedance, ZICM, are specified

so that the Ethernet specification for cable termination

impedance is met using standard 1% resistor termina-

tors. If SIP devices are used, 39 ohms is also a suitable

value. The CI

± differential inputs are terminated in

exactly the same way as the DI

± pair.

Collision Detection

A transceiver detects the collision condition on the net-

work and generates a differential signal at the CI

inputs. This collision signal passes through an input

stage which detects signal levels and pulse duration.

When the signal is detected by the MENDEC, it sets

the CLSN line HIGH. The condition continues for ap-

proximately 1.5 bit times after the last LOW-to-HIGH

transition on CI

±.

Jitter Tolerance Definition

The Receive Timing-Start of Reception Clock Acquisi-

tion waveform diagram shows the internal timing rela-

tionships implemented for decoding Manchester data

in the SIA module. The SIA utilizes a clock capture

circuit to align its internal data strobe with an incoming

bit stream. The clock acquisition circuitry requires four

valid bits with the values 1010. Clock is phase locked

to the negative transition at the bit cell center of the

second “0" in the pattern.

Since data is strobed at 1/4 bit time, Manchester tran-

sitions which shift from their nominal placement

through 1/4 bit time will result in improperly decoded

data. With this as the criteria for an error, a definition of

“Jitter Handling” is:

The peak deviation approaching or crossing 1/4 bit cell

position from nominal input transition, for which the SIA

section will properly decode data.

Attachment Unit Interface (AUI)

The AUI is the PLS (Physical Signaling) to PMA (Phys-

ical Medium Attachment) interface which effectively

connects the DTE to the MAU. The differential interface

provided by the MACE device is fully compliant to

Section 7 of ISO 8802-3 (ANSI/IEEE 802.3).

After the MACE device initiates a transmission it will

expect to see data looped-back on the DI

± pair (AUI

port selected). This will internally generate a carrier

sense, indicating that the integrity of the data path to

and from the MAU is intact, and that the MAU is oper-

ating correctly. This carrier sense signal must be

asserted during the transmission when using the AUI

port (DO

± transmitting). If carrier sense does not

become active in response to the data transmission, or

becomes inactive before the end of transmission, the

loss of carrier (LCAR) error bit will be set in the Trans-

CURIO

DI+

40.2

Ω

40.2

Ω

0.01

µF

AUI Isolation

Transformer

16235D-6

Differential Input Termination

AM79C940JC/W Datasheet(PDF) 41 Page - Advanced Micro Devices

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