AM79C940JCSLASHW datasheet(63/144 Pages) AMD

63 / 144 page

Am79C940

RCVCC (REG ADDR 27) is free

running.

RCVCCO is READ/CLEAR only.

It is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by

asserting the RESET pin or

SWRST bit.

Bit 3

RNTPCO

Runt Packet Count Overflow.

Indicates that the Runt Packet

Count register rolled over at a

value of 255 runt packets. Runt

packets are defined as received

frames which passed the inter-

nal address match criteria but

did not contain a minimum of

64-bytes of data after SFD. The

INTR pin will be activated if

the corresponding

mask

bit

RNTPCOM = 0. Note that the

RNTPC value returned in the

Receive Frame Status (RFS2)

will freeze at a value of 255,

whereas

this

based

version of RNTPC (REG ADDR

26) is free running.

RNTPCO is READ/CLEAR only.

It is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by

asserting the RESET pin or

SWRST bit.

Bit 2

MPCO

Missed Packet Count Overflow.

Indicates that the Missed Packet

Count register rolled over at a

value of 255 missed frames.

Missed frames are defined as

received frames which passed

the

internal

address

match

criteria but were missed due to a

Receive

FIFO

overflow,

the

receiver being disabled (ENRCV

= 0) or an excessive receive

frame count (RCVFC > 15). The

INTR pin will be activated if the

corresponding mask bit MPCOM

= 0.

MPCO is READ/CLEAR only. It

is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by

asserting the RESET pin or

SWRST bit.

Bit 1

RCVINT

Receive Interrupt. Indicates that

the host read the last byte/word

of a packet from the Receive

FIFO. The Receive Frame Sta-

tus is available immediately on

the next host read operation.

The INTR pin will be activated if

the

corresponding

mask

bit

RCVINTM = 0.

RCVINT is READ/CLEAR only.

It is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by acti-

vation of the RESET pin or

SWRST bit.

Bit 0

XMTINT

Transmit Interrupt. Indicates that

the MACE device has completed

the transmission of a packet and

updated the Transmit Frame

Status. The INTR pin will be

activated if the corresponding

mask bit XMTINTM = 0.

XMTINT is READ/CLEAR only.

It is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by acti-

vation of the RESET pin or

SWRST bit.

Interrupt Mask Register (IMR)

(REG ADDR 9)

This register contains the mask bits for the interrupts.

Read/write operations are permitted. Writing a one into

a bit will mask the corresponding interrupt. Writing a

zero to any previously set bit will unmask the corre-

sponding interrupt. Bit assignments for the register are

as follows:

Bit

Name

Description

Bit 7

JABM

Jabber Error Mask. JABM is the

mask for JAB. The INTR pin will

not be asserted by the MACE

device regardless of the state of

the JAB bit, if JABM is set. It is

cleared by activation of the

RESET pin or SWRST bit.

Bit 6

BABLM

Babble Error Mask. BABLM is

the mask for BABL. The INTR

pin will not be asserted by the

MACE device regardless of the

state of the BABL bit, if BABLM

is set. It is cleared by activation

of the RESET pin or SWRST bit.

Bit 5

CERRM

Collision Error Mask. CERRM is

the mask for CERR. The INTR

pin will not be asserted by the

MACE device regardless of the

state of the CERR bit, if CERRM

is set. It is cleared by activation

of the RESET pin or SWRST bit.

Bit 4

RCVCCOM Receive Collision Count Over-

flow Mask. RCVCCOM is the

mask

for

RCVCCO(Receive

Collision Count Overflow). The

INTR pin will not be asserted by

RES

BABLM

CERRM

RCVCCOM

RNTPCOM

MPCOM

RCVINTM

XMTINTM

AM79C940JC/W Datasheet(PDF) 63 Page - Advanced Micro Devices

AM79C940JC/W Datasheet(HTML) 63 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL