AM79C940JCSLASHW datasheet(72/144 Pages) AMD

72 / 144 page

Bit

Name

Description

Bit 7

RTRE

Reserved Test Register Enable.

Access to the Reserved Test

Registers should not be attempt-

ed by the user. Note that

access to the Reserved Test

to the MACE device if config-

ured in a system board appli-

cation. Access to the Reserved

Test

prevented,

regardless of the state of RTRE,

once RTRD has been set. RTRE

is cleared by activation of the

RESET pin or SWRST bit.

Bit 6

RTRD

Reserved Test Register Disable.

When

set,

access

the

Reserved

Test

Registers

inhibited, and further writes to

the

RTRD

bit

are

ignored.

Access to the Reserved Test

less of the state of RTRE, once

RTRD has been set. RTRD can

only be cleared by hardware or

software reset.

Bit 5

RPA

Runt

Packet

Accept.

Allows

receive packets which are less

than the legal minimum as spec-

ified by IEEE 802.3/Ethernet, to

be passed to the host interface

via

the

Receive

FIFO. The

receive packets must be at least

8 bytes (after SFD) in length to

be accepted. RPA is cleared by

activation of the RESET pin or

SWRST bit.

Bit 4

FCOLL

Force Collision. Allows the colli-

sion logic to be tested. The

MACE device should be in an

internal loopback test for the

FCOLL test. When FCOLL = 1, a

collision will be forced during the

next transmission attempt. This

will result in 16 total transmis-

sion attempts (if DRTRY = 0)

with the Retry Error reported in

the Transmit Frame Status reg-

ister. FCOLL is cleared by the

activation of the RESET pin or

SWRST bit.

Bit3

RCVFCSE

Receive FCS Enable. Allows the

hardware associated with the

FCS generation to be allocated

to the transmitter or receiver dur-

ing loopback diagnostics. When

clear, the FCS will be generated

and appended to the transmit

message (providing that DXMT-

FCS in the Transmit Frame Con-

trol is clear), and received after

the loopback process through

the Receive FIFO. When set, the

hardware associated with the

FCS generation is allocated to

the receiver. A transmit packet

will be assumed to contain the

FCS in the last four bytes of the

frame

passed

through

the

Transmit FIFO. The received

frame will have the FCS calcu-

lated on the data field and com-

pared with the last four bytes

contained in the received mes-

sage. An FCS error will be

flagged in the Received Status

(RFS1) if the received and cal-

culated values do not match.

RCVFCSE is only valid when in

any one of the loopback modes

as defined by LOOP [0–1]. Note

that if the receive frame is

expected to be recognized on

the basis of a multicast address

match, the FCS logic must be

allocated

the

receiver

(RCVFCSE = 1). RCVFCSE is

cleared by activation of the

RESET pin or SWRST bit.

Bit 2-1

LOOP [1-0] Loopback Control. The loopback

functions

allow

the

MACE

device to receive its own trans-

mitted frames. Three levels of

loopback are provided as shown

in the following table. During

loopback operation a multicast

address can only be recognized

if RCVFCSE = 1. LOOP [0-1] are

cleared by activation of the

RESET pin or SWRST bit

Loopback Functions

External

loopback

allow

the

MACE device to transmit to the

physical medium, using either

the AUI, 10BASE–T, DAI or

GPSI port, dependent on the

PORTSEL [1–0] bits in the PLS

Configuration Control register.

Using the internal loopback test

will ensure that transmission

Loop [1–0]

Function

No Loopback

External Loopback

Internal Loopback, excludes

MENDEC

Internal Loopback, includes

MENDEC

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