AM79C940JCSLASHW datasheet(68/144 Pages) AMD

68 / 144 page

Am79C940

PORTSEL Interface Definition

Bit 0

ENPLSIO

Enable PLS I/O. ENPLSIO is

used to enable the optional I/O

functions from the PLS function.

The following pins are affected

by the ENPLSIO bit: RXCRS,

RXDAT,

TXEN,

TXDAT+,

TXDAT-,

CLSN,

STDCLK,

RDCLK and SRD. Note that if an

external SIA is being utilized via

the GPSI, PORTSEL [1–0] = 11

must be programmed before

ENPLSIO is set, to avoid con-

tention of clock, data and/or

carrier indicator signals.

PHY Configuration

Control (PHYCC)

(REG ADDR 15)

All bits within the PHY Configuration Control register

with the exception of LNKFL, are cleared by hardware

or software reset. Bit assignments are as follows:

Bit

Name

Description

Bit 7

LNKFL

Link Fail. Reports the link integ-

rity of the 10BASE–T receiver.

When the link test function is

enabled (DLNKTST = 0), the

absence of link beat pulses on

the RXD

± pair will cause the

integrated 10BASE–T transceiv-

er to go into the link fail state. In

the link fail state, data transmis-

sion, data reception, data loop-

back and the collision detection

functions

are

disabled,

and

remain disabled until valid data

or >5 consecutive link pulses

appear on the RXD

± pair. During

link fail, the LNKFL bit will be set

and the LNKST pin should be

externally pulled HIGH. When

the link is identified as function-

al, the LNKFL bit will be cleared

and the LNKST pin is driven

LOW, which is capable of direct-

ly driving a Link OK LED. In

order to inter-operate with sys-

tems which do not implement

Link Test, this function can be

disabled

setting

the

DLNKTST bit. With Link Test

disabled (DLNKTST = 1), the

data driver, receiver and loop-

back functions as well as colli-

sion detection remain enabled

irrespective of the presence or

absence of data or link pulses on

the RXD

± pair. The transmitter

will continue to generate link

beat pulses during periods of

transmit data inactivity. Set by

hardware or software reset.

Bit 6

DLNKTST

Disable Link Test. When set, the

integrated 10BASE–T transceiv-

er will be forced into the link pass

state, regardless of receive link

test pulses or receive packet

activity.

Bit 5

REVPOL

Reversed Polarity. Indicates the

receive polarity of the RD

± pair.

When normal polarity is detect-

ed, the REVPOL bit will be

cleared, and the RXPOL pin

(capable of driving a Polarity OK

LED) will be driven LOW. When

reverse polarity is detected, the

REVPOL bit will be set, and the

RXPOL pin should be externally

pulled HIGH.

Bit 4

DAPC

Disable Auto Polarity Correction.

When set, the automatic polarity

correction

will

disabled.

Polarity detection and indication

will still be possible via the

RXPOL pin.

Bit 3

LRT

Low Receive Threshold. When

set, the threshold of the twisted

pair receiver will be reduced by

4.5 dB, to allow extended dis-

tance operation.

Bit 2

ASEL

Auto Select. When set, the

PORTSEL [1-0] bits are overrid-

den, and the MACE device will

automatically select the operat-

ing media interface port. When

the 10BASE–T transceiver is in

the link pass state (due to receiv-

ing valid packet data and/or Link

Test pulses or the DLNKTST bit

is set), the 10BASE-T port will be

used. When the 10BASE–T port

is in the link fail state, the AUI

port will be used. Switching

between the ports will not occur

during transmission in order to

avoid any type of fragment

generation.

Bit 1

RWAKE

Remote Wake. When set prior to

the SLEEP pin being activated,

the AUI and 10BASE–T receiver

sections and the EADI port will

PORTSEL

[1–0]

Active

Interface

DXCVR Pin

AUI

LOW

10BASE–THIGH

DAI Port

HIGH

GPSI

LOW

LNKFL

DLNKTST

REVPOL

DAPC

LRT

ASEL

RWAKE

AWAKE

AM79C940JC/W Datasheet(PDF) 68 Page - Advanced Micro Devices

AM79C940JC/W Datasheet(HTML) 68 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL