AM79C940JCSLASHW datasheet(59/144 Pages) AMD

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Am79C940

re-asserted until the XMTFS has

been read. The MACE device

does not retry after a late

collision.

Bit 4

More. Indicates that more than

one retry was needed to transmit

the frame. ONE, MORE and

RTRY are mutually exclusive.

Bit 3

ONE

One. Indicates that exactly one

retry was needed to transmit the

frame. ONE, MORE and RTRY

are mutually exclusive.

Bit 2

DEFER

Defer.

Indicates

that

MACE

device had to defer transmission

of the frame. This condition

results if the channel is busy

when the MACE device is ready

to transmit.

Bit 1

LCAR

Loss of Carrier. Indicates that

the carrier became false during

transmission.

The

MACE

device does not retry upon Loss

of Carrier. LCAR will not be set

when the DAI port is selected,

when the 10BASE-T port is se-

lected and in the link pass state,

or during any internal loopback

mode. When the 10BASE-T port

is selected and in the link fail

state, LCAR will will be reported

for any transmission attempt.

Bit 0

RTRY

Retry Error. Indicates that all

attempts to transmit the frame

were unsuccessful, and that fur-

ther attempts have been abort-

ed. If Disable Retry (DRTRY in

the Transmit Frame Control reg-

ister) is cleared, RTRY will be

set when a total of 16 unsuc-

cessful attempts were made to

transmit the frame. If DRTRY is

set, RTRY indicates that the first

and only attempt to transmit the

frame was unsuccessful. ONE,

MORE and RTRY are mutually

exclusive.

RTRY

set,

TDTREQ will be de-asserted,

and will not be re-asserted until

the XMTFS has been read.

Transmit Retry Count (XMTRC)

(REG ADDR 4)

The Transmit Retry Count should be read only in

response to a hardware interrupt request (INTR

asserted) when XMTINT is set in the Interrupt Register,

or after XMTSV is set in the Poll Register.The register

should be read before the Transmit Frame Status

XMTSV set will cause the XMTRC value to be reset.

This register is read only.

Bit

Name

Description

Bit 3-0

EXDEF

Excessive Defer. The EXDEF bit

will be set if a transmit frame

waited for an excessive period

for transmission. An excessive

defer time is defined in accor-

dance with the following (from

page 34, section 5.2.4.1 of IEEE

Std 802.3h-1990 Layer Manage-

ment):maxDeferTime

(max frame size x 8)} bits where

maxFrameSize = 1518 bytes

(from page 68, section 4.4.2.1 of

ANSI/IEEE

Std

802.3-1990).

So, the maxDeferTime = 24288

bits = 214+ 212 + 211+ 210 + 29

7 +26 +25

Bit 6-4

RES

Reserved.

Read

zeroes.

Always write as zeroes.

Bit 3-0

XMTRCTransmit Retry Count.

Contains

[3-0]

the count of the number of retry

attempts made by the MACE

device to transmit the current

transmit packet. The value of the

counter will be zero if the first

transmission attempt was suc-

cessful, and a maximum of 15 if

all retry attempts were utilized.

RTRY will be set in Transmit

Frame Status if all 16 attempts

were unsuccessful.

Receive Frame Control (RCVFC)

(REG ADDR 5)

Bit

Name

Description

Bit 7-4

RES

Reserved.

Read

zeroes.

Always write as zeroes.

Bit 3

LLRCV

Low

Latency

Receive.

programmable option to allow

access to the Receive FIFO

before the 64-byte threshold has

been reached. When set, data

can be read from the RCVFIFO

once a low threshold (12-bytes

after SFD plus synchronization)

has been exceeded, causing

RDTREQ

asserted.

RDTREQ will remain asserted

as long as one read cycle can be

performed

the

RCVFIFO

(identical to the burst mode).

Indication of a valid read cycle

from the RCVFIFO will return

DTV

asserted.

Reading

the

RCVFIFO before data is avail-

able, or while waiting for addi-

EXDEF

RES

XMTRC[3-0]

RES

LLRCV

M/R

RES

ASTRPRCV

AM79C940JC/W Datasheet(PDF) 59 Page - Advanced Micro Devices

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