AM79C940JCSLASHW datasheet(32/144 Pages) AMD

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Am79C940

that the last byte is transferred over is irrelevant,

providing the appropriate byte enable is used. For

BSWP = 0, data can be presented on DBUS7-0

using BE0 or DBUS15-8 using BE1. For BSWP =

1, data can be presented on DBUS7-0 using BE1

or DBUS15-8 using BE0.

(f) When neither BE0 nor BE1 are asserted, no data

transfer will take place. DTV will not be asserted.

Byte Alignment For FIFO Read Operations

Byte Alignment For FIFO Write Operations

BIU to Control and Status

All registers in the address range 2-31 are 8-bits wide.

When a read cycle is executed on any of these regis-

ters, the MACE device will drive data on both bytes of

the data bus, regardless of the programming of BSWP.

When a write cycle is executed, the MACE device

strobes in data based on the programming of BSWP as

shown in the tables below. All accesses to addresses

2-31 are independent of the BE0 and BE1 pins.

Byte Alignment For Register Read Operations

Byte Alignment For Register Write Operations

FIFO Subsystem

The MACE device has two independent FIFOs, with

128-bytes for receive and 136-bytes for transmit oper-

ations. The FIFO sub-system contains both the FIFOs,

and the control logic to handle normal and exception

related conditions.

The Transmit and Receive FIFOs interface on the net-

work side with the serializer/de-serializer in the MAC

engine. The BIU provides access between the FIFOs

and the host system to enable the movement of data to

and from the network.

Internally, the FIFOs appear to the BIU as independent

16-bit wide registers. Bytes or words can be written to

the Transmit FIFO (XMTFIFO), or read from the

Receive FIFO (RCVFIFO). Byte and word transfers

can be mixed in any order. The BIU will ensure correct

byte ordering dependent on the target host system, as

determined by the programming of the BSWP bit in the

BIU Configuration Control register.

The XMTFIFO and RCVFIFO have three different

modes of operation. These are Normal (Default), Burst

and Low Latency Receive. Default operation will be

used after the hardware RESET pin or software

SWRST bit have been activated. The remainder of this

general description applies to all modes except where

specific differences are noted.

Transmit FIFO—General Operation

When writing bytes to the XMTFIFO, certain restric-

tions apply. These restrictions have a direct influence

on the latency provided by the FIFO to the host system.

When a byte is written to the FIFO location, the entire

word location is used. The unused byte is marked as a

hole in the XMTFIFO. These holes are skipped during

the serialization process performed by the MAC

engine, when the bytes are unloaded from the

XMTFIFO.

For instance, assume the Transmit FIFO Watermark

(XMTFW) is set for 32 write cycles. If the host writes

byte wide data to the XMTFIFO, after 36 write cycles

there will be space left in the XMTFIFO for only 32

more write cycles. Therefore TDTREQ will de-assert

even though only 36-bytes of data have been loaded

into the XMTFIFO. Transmission will not commence

until 64-bytes or the End-of-Frame are available in the

XMFIFO, so transmission would not start, and

BE0

BE1

BSWP

DBUS7-0

DBUS15-8

n+1

BE0

BE1

BSWP

DBUS7-0

DBUS15-8

n+1

BE0

BE1

BSWP

DBUS7-0

DBUS15-8

Read

Data

Read

Data

Read

Data

Read

Data

BE0

BE1

BSWP

DBUS7-0

DBUS15-8

Write

Data

Write

Data

AM79C940JC/W Datasheet(PDF) 32 Page - Advanced Micro Devices

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