AM79C940JCSLASHW datasheet(44/144 Pages) AMD

44 / 144 page

Am79C940

Positive Link Test pulses are defined as received signal

with a positive amplitude greater than 520 mV (LRT =

LOW) with a pulse width of 60 ns-200 ns. This positive

excursion may be followed by a negative excursion.

This definition is consistent with the expected received

signal at a correctly wired receiver, when a Link Test

pulse which fits the template of Figure 14-12 in the

10BASE-T Standard is generated at a transmitter and

passed through 100 m of twisted pair cable.

Negative Link Test pulses are defined as received sig-

nals with a negative amplitude greater than 520 mV

(LRT = LOW) with a pulse width of 60 ns-200 ns. This

negative excursion may be followed by a positive ex-

cursion. This definition is consistent with the expected

received signal at a reverse wired receiver, when a

Link Test pulse which fits the template of Figure 14-12

in the 10BASE–T Standard is generated at a transmit-

ter and passed through 100 m of twisted pair cable.

The polarity detection/correction algorithm will remain

armed until two consecutive packets with valid ETD of

identical polarity are detected. When armed, the

receiver is capable of changing the initial or previous

polarity configuration based on the most recent ETD

polarity.

On receipt of the first packet with valid ETD following

reset or Link Fail, the MACE device will utilize the

inferred polarity information to configure its RXD

input, regardless of its previous state. On receipt of a

second packet with a valid ETD with correct polarity,

the detection/correction algorithm will lock-in the

received polarity. If the second (or subsequent) packet

is not detected as confirming the previous polarity

decision, the most recently detected ETD polarity will

be used as the default. Note that packets with invalid

ETD have no effect on updating the previous polarity

decision. Once two consecutive packets with valid ETD

have been received, the MACE device will disable the

detection/correction algorithm until either a Link Fail

condition occurs or a hardware or software reset

occurs.

During polarity reversal, the RXPOL pin should be

externally pulled HIGH and the Reversed Polarity bit

(REVPOL in the PHY Configuration Control register)

will be set. During normal polarity conditions, the

RXPOL pin is driven LOW (capable of directly driving a

Polarity OK LED using an integrated 12 mA driver) and

the REVPOL bit will be cleared.

If desired, the polarity correction function can be dis-

abled by setting the Disable Auto Polarity Correction bit

(DAPC bit in the PHY Configuration Control register).

However, the polarity detection portion of the algorithm

continues to operate independently, and the RXPOL

pin and the REVPOL bits will reflect the polarity state of

the receiver.

Twisted Pair Interface Status

Three outputs (TXEN, RXCRS and CLSN) indicate

whether the MACE device is transmitting (MENDECto

Twisted Pair), receiving (Twisted Pair to MENDEC), or

in a collision state with both func tions activ e

simultaneously.

The MACE device will power up in the Link Fail state.

The normal algorithm will apply to allow it to enter the

Link Pass state. On power up, the TXEN, RXCRS and

CLSN) pins will be in a high impedance state until they

are enabled by setting the Enable PLS I/O bit

(ENPLSIO in the PLS Configuration Control register)

and the 10BASE-T port enters the Link Pass state.

In the Link Pass state, transmit or receive activity which

passes the pulse width/amplitude requirements of the

± or RXD± inputs, will be indicated by the TXEN or

RXCRS pin respectively going active. TXEN, RXCRS

and CLSN are all asserted during a collision.

In the Link Fail state, TXEN, RXCRS and CLSN

are inactive.

In jabber detect mode, the MACE device will activate

the CLSN pin, disable TXEN (regardless of Manches-

ter data output from the MENDEC), and allow the

RXCRS pin to indicate the current state of the RXD

pair. If there is no receive activity on RXD

±, only CLSN

will be active during jabber detect. If there is RXD

± ac-

tivity, both CLSN and RXCRS will be active.

If the SLEEP pin is asserted (regardless of the pro-

gramming of the AWAKE or RWAKE bits in the PHY

Configuration Control register), the TXEN, RXCRS and

CLSN outputs will be placed in a high impedance state.

Collision Detect Function

Simultaneous activity (presence of valid data signals)

from both the internal MENDEC transmit function (indi-

cated externally by TXEN active) and the twisted pair

RXD

± pins constitutes a collision, thereby causing an

external indication on the CLSN pin, and an internal

indication which is returned to the MAC core. The

TXEN, RXCRS and CLSN pins are driven high during

collision.

Signal Quality Error (SQE) Test (Heartbeat)

Function

The SQE Test message (a 10 MHz burst normally

returned on the AUI CI

± pair at the end of every trans-

mission) is intended to be a self-test indication to the

DTE that the MAU collision circuitry is functional and

the AUI cable/connection is intact. This has minimal

relevance when the 10BASE-T MAU is embedded in

the LAN controller. A Collision Error (CERR bit in the In-

terrupt Register) will be reported only when the

10BASE-T port is in the link fail state, since the collision

circuit of the MAU will be disabled, causing the

absence of the SQE Test message. In GPSI mode the

AM79C940JC/W Datasheet(PDF) 44 Page - Advanced Micro Devices

AM79C940JC/W Datasheet(HTML) 44 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL